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<h1 class="heading">wr_transmission_wb</h1>
<h3>WR Transmission control, status and debug</h3>
<p><br>  -----------------------------------------------------------------<br>  This WB registers allow to diagnose transmission and reception of<br>  data using WR streamers.                                         <br>  In particular, these registers provide access to streamer's      <br>  statistics that can be also access from SNMP, if supported.      <br>  -----------------------------------------------------------------<br>  Copyright (c) 2016 CERN/BE-CO-HT & CERN/TE-MS-MM                 <br>                                                                   <br>  This source file is free software; you can redistribute it       <br>  and/or modify it under the terms of the GNU Lesser General       <br>  Public License as published by the Free Software Foundation;     <br>  either version 2.1 of the License, or (at your option) any       <br>  later version.                                                   <br>                                                                   <br>  This source is distributed in the hope that it will be           <br>  useful, but WITHOUT ANY WARRANTY; without even the implied       <br>  warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR          <br>  PURPOSE.  See the GNU Lesser General Public License for more     <br>  details                                                          <br>                                                                   <br>  You should have received a copy of the GNU Lesser General        <br>  Public License along with this source; if not, download it       <br>  from http://www.gnu.org/licenses/lgpl-2.1.html                   <br>  -----------------------------------------------------------------</p>
<h3>Contents:</h3>
<span style="margin-left: 0px; ">1. <A href="#sect_1_0">Memory map summary</a></span><br/>
<span style="margin-left: 0px; ">2. <A href="#sect_2_0">HDL symbol</a></span><br/>
<span style="margin-left: 0px; ">3. <A href="#sect_3_0">Register description</a></span><br/>
<span style="margin-left: 20px; ">3.1. <A href="#sect_3_1">Statistics status and ctrl register</a></span><br/>
<span style="margin-left: 20px; ">3.2. <A href="#sect_3_2">Statistics status and ctrl register</a></span><br/>
<span style="margin-left: 20px; ">3.3. <A href="#sect_3_3">Tx statistics</a></span><br/>
<span style="margin-left: 20px; ">3.4. <A href="#sect_3_4">Rx statistics</a></span><br/>
<span style="margin-left: 20px; ">3.5. <A href="#sect_3_5">Rx statistics</a></span><br/>
<span style="margin-left: 20px; ">3.6. <A href="#sect_3_6">Rx statistics</a></span><br/>
<span style="margin-left: 20px; ">3.7. <A href="#sect_3_7">Rx statistics</a></span><br/>
<span style="margin-left: 20px; ">3.8. <A href="#sect_3_8">Rx statistics</a></span><br/>
<span style="margin-left: 20px; ">3.9. <A href="#sect_3_9">Rx statistics</a></span><br/>
<span style="margin-left: 20px; ">3.10. <A href="#sect_3_10">Rx statistics</a></span><br/>
<span style="margin-left: 20px; ">3.11. <A href="#sect_3_11">Rx statistics</a></span><br/>
<span style="margin-left: 20px; ">3.12. <A href="#sect_3_12">Tx Config Reg 0</a></span><br/>
<span style="margin-left: 20px; ">3.13. <A href="#sect_3_13">Tx Config Reg 1</a></span><br/>
<span style="margin-left: 20px; ">3.14. <A href="#sect_3_14">Tx Config Reg 2</a></span><br/>
<span style="margin-left: 20px; ">3.15. <A href="#sect_3_15">Tx Config Reg 3</a></span><br/>
<span style="margin-left: 20px; ">3.16. <A href="#sect_3_16">Tx Config Reg 4</a></span><br/>
<span style="margin-left: 20px; ">3.17. <A href="#sect_3_17">Rx Config Reg 0</a></span><br/>
<span style="margin-left: 20px; ">3.18. <A href="#sect_3_18">Rx Config Reg 1</a></span><br/>
<span style="margin-left: 20px; ">3.19. <A href="#sect_3_19">Rx Config Reg 2</a></span><br/>
<span style="margin-left: 20px; ">3.20. <A href="#sect_3_20">Rx Config Reg 3</a></span><br/>
<span style="margin-left: 20px; ">3.21. <A href="#sect_3_21">Rx Config Reg 4</a></span><br/>
<span style="margin-left: 20px; ">3.22. <A href="#sect_3_22">Rx Config Reg 5</a></span><br/>
<span style="margin-left: 20px; ">3.23. <A href="#sect_3_23">TxRx Config Override</a></span><br/>
<span style="margin-left: 20px; ">3.24. <A href="#sect_3_24">DBG Control register</a></span><br/>
<span style="margin-left: 20px; ">3.25. <A href="#sect_3_25">DBG Data</a></span><br/>
<span style="margin-left: 20px; ">3.26. <A href="#sect_3_26">DBG RX_BVALUE</a></span><br/>
<span style="margin-left: 20px; ">3.27. <A href="#sect_3_27">DBG tx bvalue</a></span><br/>
<span style="margin-left: 20px; ">3.28. <A href="#sect_3_28">Test value</a></span><br/>
<h3><a name="sect_1_0">1. Memory map summary</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<th >
H/W Address
</th>
<th >
Type
</th>
<th >
Name
</th>
<th >
VHDL/Verilog prefix
</th>
<th >
C prefix
</th>
</tr>
<tr class="tr_odd">
<td  class="td_code">
0x0
</td>
<td >
REG
</td>
<td >
<A href="#SSCR1">Statistics status and ctrl register</a>
</td>
<td  class="td_code">
wr_transmission_sscr1
</td>
<td  class="td_code">
SSCR1
</td>
</tr>
<tr class="tr_even">
<td  class="td_code">
0x1
</td>
<td >
REG
</td>
<td >
<A href="#SSCR2">Statistics status and ctrl register</a>
</td>
<td  class="td_code">
wr_transmission_sscr2
</td>
<td  class="td_code">
SSCR2
</td>
</tr>
<tr class="tr_odd">
<td  class="td_code">
0x2
</td>
<td >
REG
</td>
<td >
<A href="#TX_STAT">Tx statistics</a>
</td>
<td  class="td_code">
wr_transmission_tx_stat
</td>
<td  class="td_code">
TX_STAT
</td>
</tr>
<tr class="tr_even">
<td  class="td_code">
0x3
</td>
<td >
REG
</td>
<td >
<A href="#RX_STAT1">Rx statistics</a>
</td>
<td  class="td_code">
wr_transmission_rx_stat1
</td>
<td  class="td_code">
RX_STAT1
</td>
</tr>
<tr class="tr_odd">
<td  class="td_code">
0x4
</td>
<td >
REG
</td>
<td >
<A href="#RX_STAT2">Rx statistics</a>
</td>
<td  class="td_code">
wr_transmission_rx_stat2
</td>
<td  class="td_code">
RX_STAT2
</td>
</tr>
<tr class="tr_even">
<td  class="td_code">
0x5
</td>
<td >
REG
</td>
<td >
<A href="#RX_STAT3">Rx statistics</a>
</td>
<td  class="td_code">
wr_transmission_rx_stat3
</td>
<td  class="td_code">
RX_STAT3
</td>
</tr>
<tr class="tr_odd">
<td  class="td_code">
0x6
</td>
<td >
REG
</td>
<td >
<A href="#RX_STAT4">Rx statistics</a>
</td>
<td  class="td_code">
wr_transmission_rx_stat4
</td>
<td  class="td_code">
RX_STAT4
</td>
</tr>
<tr class="tr_even">
<td  class="td_code">
0x7
</td>
<td >
REG
</td>
<td >
<A href="#RX_STAT5">Rx statistics</a>
</td>
<td  class="td_code">
wr_transmission_rx_stat5
</td>
<td  class="td_code">
RX_STAT5
</td>
</tr>
<tr class="tr_odd">
<td  class="td_code">
0x8
</td>
<td >
REG
</td>
<td >
<A href="#RX_STAT6">Rx statistics</a>
</td>
<td  class="td_code">
wr_transmission_rx_stat6
</td>
<td  class="td_code">
RX_STAT6
</td>
</tr>
<tr class="tr_even">
<td  class="td_code">
0x9
</td>
<td >
REG
</td>
<td >
<A href="#RX_STAT7">Rx statistics</a>
</td>
<td  class="td_code">
wr_transmission_rx_stat7
</td>
<td  class="td_code">
RX_STAT7
</td>
</tr>
<tr class="tr_odd">
<td  class="td_code">
0xa
</td>
<td >
REG
</td>
<td >
<A href="#RX_STAT8">Rx statistics</a>
</td>
<td  class="td_code">
wr_transmission_rx_stat8
</td>
<td  class="td_code">
RX_STAT8
</td>
</tr>
<tr class="tr_even">
<td  class="td_code">
0xb
</td>
<td >
REG
</td>
<td >
<A href="#TX_CFG0">Tx Config Reg 0</a>
</td>
<td  class="td_code">
wr_transmission_tx_cfg0
</td>
<td  class="td_code">
TX_CFG0
</td>
</tr>
<tr class="tr_odd">
<td  class="td_code">
0xc
</td>
<td >
REG
</td>
<td >
<A href="#TX_CFG1">Tx Config Reg 1</a>
</td>
<td  class="td_code">
wr_transmission_tx_cfg1
</td>
<td  class="td_code">
TX_CFG1
</td>
</tr>
<tr class="tr_even">
<td  class="td_code">
0xd
</td>
<td >
REG
</td>
<td >
<A href="#TX_CFG2">Tx Config Reg 2</a>
</td>
<td  class="td_code">
wr_transmission_tx_cfg2
</td>
<td  class="td_code">
TX_CFG2
</td>
</tr>
<tr class="tr_odd">
<td  class="td_code">
0xe
</td>
<td >
REG
</td>
<td >
<A href="#TX_CFG3">Tx Config Reg 3</a>
</td>
<td  class="td_code">
wr_transmission_tx_cfg3
</td>
<td  class="td_code">
TX_CFG3
</td>
</tr>
<tr class="tr_even">
<td  class="td_code">
0xf
</td>
<td >
REG
</td>
<td >
<A href="#TX_CFG4">Tx Config Reg 4</a>
</td>
<td  class="td_code">
wr_transmission_tx_cfg4
</td>
<td  class="td_code">
TX_CFG4
</td>
</tr>
<tr class="tr_odd">
<td  class="td_code">
0x10
</td>
<td >
REG
</td>
<td >
<A href="#RX_CFG0">Rx Config Reg 0</a>
</td>
<td  class="td_code">
wr_transmission_rx_cfg0
</td>
<td  class="td_code">
RX_CFG0
</td>
</tr>
<tr class="tr_even">
<td  class="td_code">
0x11
</td>
<td >
REG
</td>
<td >
<A href="#RX_CFG1">Rx Config Reg 1</a>
</td>
<td  class="td_code">
wr_transmission_rx_cfg1
</td>
<td  class="td_code">
RX_CFG1
</td>
</tr>
<tr class="tr_odd">
<td  class="td_code">
0x12
</td>
<td >
REG
</td>
<td >
<A href="#RX_CFG2">Rx Config Reg 2</a>
</td>
<td  class="td_code">
wr_transmission_rx_cfg2
</td>
<td  class="td_code">
RX_CFG2
</td>
</tr>
<tr class="tr_even">
<td  class="td_code">
0x13
</td>
<td >
REG
</td>
<td >
<A href="#RX_CFG3">Rx Config Reg 3</a>
</td>
<td  class="td_code">
wr_transmission_rx_cfg3
</td>
<td  class="td_code">
RX_CFG3
</td>
</tr>
<tr class="tr_odd">
<td  class="td_code">
0x14
</td>
<td >
REG
</td>
<td >
<A href="#RX_CFG4">Rx Config Reg 4</a>
</td>
<td  class="td_code">
wr_transmission_rx_cfg4
</td>
<td  class="td_code">
RX_CFG4
</td>
</tr>
<tr class="tr_even">
<td  class="td_code">
0x15
</td>
<td >
REG
</td>
<td >
<A href="#RX_CFG5">Rx Config Reg 5</a>
</td>
<td  class="td_code">
wr_transmission_rx_cfg5
</td>
<td  class="td_code">
RX_CFG5
</td>
</tr>
<tr class="tr_odd">
<td  class="td_code">
0x16
</td>
<td >
REG
</td>
<td >
<A href="#CFG">TxRx Config Override</a>
</td>
<td  class="td_code">
wr_transmission_cfg
</td>
<td  class="td_code">
CFG
</td>
</tr>
<tr class="tr_even">
<td  class="td_code">
0x17
</td>
<td >
REG
</td>
<td >
<A href="#DBG_CTRL">DBG Control register</a>
</td>
<td  class="td_code">
wr_transmission_dbg_ctrl
</td>
<td  class="td_code">
DBG_CTRL
</td>
</tr>
<tr class="tr_odd">
<td  class="td_code">
0x18
</td>
<td >
REG
</td>
<td >
<A href="#DBG_DATA">DBG Data</a>
</td>
<td  class="td_code">
wr_transmission_dbg_data
</td>
<td  class="td_code">
DBG_DATA
</td>
</tr>
<tr class="tr_even">
<td  class="td_code">
0x19
</td>
<td >
REG
</td>
<td >
<A href="#DBG_RX_BVALUE">DBG RX_BVALUE</a>
</td>
<td  class="td_code">
wr_transmission_dbg_rx_bvalue
</td>
<td  class="td_code">
DBG_RX_BVALUE
</td>
</tr>
<tr class="tr_odd">
<td  class="td_code">
0x1a
</td>
<td >
REG
</td>
<td >
<A href="#DBG_TX_BVALUE">DBG tx bvalue</a>
</td>
<td  class="td_code">
wr_transmission_dbg_tx_bvalue
</td>
<td  class="td_code">
DBG_TX_BVALUE
</td>
</tr>
<tr class="tr_even">
<td  class="td_code">
0x1b
</td>
<td >
REG
</td>
<td >
<A href="#DUMMY">Test value</a>
</td>
<td  class="td_code">
wr_transmission_dummy
</td>
<td  class="td_code">
DUMMY
</td>
</tr>
</table>

<h3><a name="sect_2_0">2. HDL symbol</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td  class="td_arrow_left">
&rarr;
</td>
<td  class="td_pblock_left">
rst_n_i
</td>
<td  class="td_sym_center">

</td>
<td  class="td_pblock_right">
<b>Statistics status and ctrl register:</b>
</td>
<td  class="td_arrow_right">

</td>
</tr>
<tr>
<td  class="td_arrow_left">
&rarr;
</td>
<td  class="td_pblock_left">
clk_sys_i
</td>
<td  class="td_sym_center">

</td>
<td  class="td_pblock_right">
wr_transmission_sscr1_rst_stats_o
</td>
<td  class="td_arrow_right">
&rarr;
</td>
</tr>
<tr>
<td  class="td_arrow_left">
&rArr;
</td>
<td  class="td_pblock_left">
wb_adr_i[4:0]
</td>
<td  class="td_sym_center">

</td>
<td  class="td_pblock_right">
wr_transmission_sscr1_rst_seq_id_o
</td>
<td  class="td_arrow_right">
&rarr;
</td>
</tr>
<tr>
<td  class="td_arrow_left">
&rArr;
</td>
<td  class="td_pblock_left">
wb_dat_i[31:0]
</td>
<td  class="td_sym_center">

</td>
<td  class="td_pblock_right">
wr_transmission_sscr1_snapshot_stats_o
</td>
<td  class="td_arrow_right">
&rarr;
</td>
</tr>
<tr>
<td  class="td_arrow_left">
&lArr;
</td>
<td  class="td_pblock_left">
wb_dat_o[31:0]
</td>
<td  class="td_sym_center">

</td>
<td  class="td_pblock_right">
wr_transmission_sscr1_rx_latency_acc_overflow_i
</td>
<td  class="td_arrow_right">
&larr;
</td>
</tr>
<tr>
<td  class="td_arrow_left">
&rarr;
</td>
<td  class="td_pblock_left">
wb_cyc_i
</td>
<td  class="td_sym_center">

</td>
<td  class="td_pblock_right">
wr_transmission_sscr1_rst_ts_cyc_i[27:0]
</td>
<td  class="td_arrow_right">
&lArr;
</td>
</tr>
<tr>
<td  class="td_arrow_left">
&rArr;
</td>
<td  class="td_pblock_left">
wb_sel_i[3:0]
</td>
<td  class="td_sym_center">
&nbsp;
</td>
<td  class="td_pblock_right">

</td>
<td  class="td_arrow_right">

</td>
</tr>
<tr>
<td  class="td_arrow_left">
&rarr;
</td>
<td  class="td_pblock_left">
wb_stb_i
</td>
<td  class="td_sym_center">

</td>
<td  class="td_pblock_right">
<b>Statistics status and ctrl register:</b>
</td>
<td  class="td_arrow_right">

</td>
</tr>
<tr>
<td  class="td_arrow_left">
&rarr;
</td>
<td  class="td_pblock_left">
wb_we_i
</td>
<td  class="td_sym_center">

</td>
<td  class="td_pblock_right">
wr_transmission_sscr2_rst_ts_tai_lsb_i[31:0]
</td>
<td  class="td_arrow_right">
&lArr;
</td>
</tr>
<tr>
<td  class="td_arrow_left">
&larr;
</td>
<td  class="td_pblock_left">
wb_ack_o
</td>
<td  class="td_sym_center">
&nbsp;
</td>
<td  class="td_pblock_right">

</td>
<td  class="td_arrow_right">

</td>
</tr>
<tr>
<td  class="td_arrow_left">
&larr;
</td>
<td  class="td_pblock_left">
wb_stall_o
</td>
<td  class="td_sym_center">

</td>
<td  class="td_pblock_right">
<b>Tx statistics:</b>
</td>
<td  class="td_arrow_right">

</td>
</tr>
<tr>
<td  class="td_arrow_left">

</td>
<td  class="td_pblock_left">

</td>
<td  class="td_sym_center">

</td>
<td  class="td_pblock_right">
wr_transmission_tx_stat_tx_sent_cnt_i[31:0]
</td>
<td  class="td_arrow_right">
&lArr;
</td>
</tr>
<tr>
<td  class="td_arrow_left">

</td>
<td  class="td_pblock_left">

</td>
<td  class="td_sym_center">
&nbsp;
</td>
<td  class="td_pblock_right">

</td>
<td  class="td_arrow_right">

</td>
</tr>
<tr>
<td  class="td_arrow_left">

</td>
<td  class="td_pblock_left">

</td>
<td  class="td_sym_center">

</td>
<td  class="td_pblock_right">
<b>Rx statistics:</b>
</td>
<td  class="td_arrow_right">

</td>
</tr>
<tr>
<td  class="td_arrow_left">

</td>
<td  class="td_pblock_left">

</td>
<td  class="td_sym_center">

</td>
<td  class="td_pblock_right">
wr_transmission_rx_stat1_rx_rcvd_cnt_i[31:0]
</td>
<td  class="td_arrow_right">
&lArr;
</td>
</tr>
<tr>
<td  class="td_arrow_left">

</td>
<td  class="td_pblock_left">

</td>
<td  class="td_sym_center">
&nbsp;
</td>
<td  class="td_pblock_right">

</td>
<td  class="td_arrow_right">

</td>
</tr>
<tr>
<td  class="td_arrow_left">

</td>
<td  class="td_pblock_left">

</td>
<td  class="td_sym_center">

</td>
<td  class="td_pblock_right">
<b>Rx statistics:</b>
</td>
<td  class="td_arrow_right">

</td>
</tr>
<tr>
<td  class="td_arrow_left">

</td>
<td  class="td_pblock_left">

</td>
<td  class="td_sym_center">

</td>
<td  class="td_pblock_right">
wr_transmission_rx_stat2_rx_loss_cnt_i[31:0]
</td>
<td  class="td_arrow_right">
&lArr;
</td>
</tr>
<tr>
<td  class="td_arrow_left">

</td>
<td  class="td_pblock_left">

</td>
<td  class="td_sym_center">
&nbsp;
</td>
<td  class="td_pblock_right">

</td>
<td  class="td_arrow_right">

</td>
</tr>
<tr>
<td  class="td_arrow_left">

</td>
<td  class="td_pblock_left">

</td>
<td  class="td_sym_center">

</td>
<td  class="td_pblock_right">
<b>Rx statistics:</b>
</td>
<td  class="td_arrow_right">

</td>
</tr>
<tr>
<td  class="td_arrow_left">

</td>
<td  class="td_pblock_left">

</td>
<td  class="td_sym_center">

</td>
<td  class="td_pblock_right">
wr_transmission_rx_stat3_rx_latency_max_i[27:0]
</td>
<td  class="td_arrow_right">
&lArr;
</td>
</tr>
<tr>
<td  class="td_arrow_left">

</td>
<td  class="td_pblock_left">

</td>
<td  class="td_sym_center">
&nbsp;
</td>
<td  class="td_pblock_right">

</td>
<td  class="td_arrow_right">

</td>
</tr>
<tr>
<td  class="td_arrow_left">

</td>
<td  class="td_pblock_left">

</td>
<td  class="td_sym_center">

</td>
<td  class="td_pblock_right">
<b>Rx statistics:</b>
</td>
<td  class="td_arrow_right">

</td>
</tr>
<tr>
<td  class="td_arrow_left">

</td>
<td  class="td_pblock_left">

</td>
<td  class="td_sym_center">

</td>
<td  class="td_pblock_right">
wr_transmission_rx_stat4_rx_latency_min_i[27:0]
</td>
<td  class="td_arrow_right">
&lArr;
</td>
</tr>
<tr>
<td  class="td_arrow_left">

</td>
<td  class="td_pblock_left">

</td>
<td  class="td_sym_center">
&nbsp;
</td>
<td  class="td_pblock_right">

</td>
<td  class="td_arrow_right">

</td>
</tr>
<tr>
<td  class="td_arrow_left">

</td>
<td  class="td_pblock_left">

</td>
<td  class="td_sym_center">

</td>
<td  class="td_pblock_right">
<b>Rx statistics:</b>
</td>
<td  class="td_arrow_right">

</td>
</tr>
<tr>
<td  class="td_arrow_left">

</td>
<td  class="td_pblock_left">

</td>
<td  class="td_sym_center">

</td>
<td  class="td_pblock_right">
wr_transmission_rx_stat5_rx_latency_acc_lsb_i[31:0]
</td>
<td  class="td_arrow_right">
&lArr;
</td>
</tr>
<tr>
<td  class="td_arrow_left">

</td>
<td  class="td_pblock_left">

</td>
<td  class="td_sym_center">
&nbsp;
</td>
<td  class="td_pblock_right">

</td>
<td  class="td_arrow_right">

</td>
</tr>
<tr>
<td  class="td_arrow_left">

</td>
<td  class="td_pblock_left">

</td>
<td  class="td_sym_center">

</td>
<td  class="td_pblock_right">
<b>Rx statistics:</b>
</td>
<td  class="td_arrow_right">

</td>
</tr>
<tr>
<td  class="td_arrow_left">

</td>
<td  class="td_pblock_left">

</td>
<td  class="td_sym_center">

</td>
<td  class="td_pblock_right">
wr_transmission_rx_stat6_rx_latency_acc_msb_i[31:0]
</td>
<td  class="td_arrow_right">
&lArr;
</td>
</tr>
<tr>
<td  class="td_arrow_left">

</td>
<td  class="td_pblock_left">

</td>
<td  class="td_sym_center">
&nbsp;
</td>
<td  class="td_pblock_right">

</td>
<td  class="td_arrow_right">

</td>
</tr>
<tr>
<td  class="td_arrow_left">

</td>
<td  class="td_pblock_left">

</td>
<td  class="td_sym_center">

</td>
<td  class="td_pblock_right">
<b>Rx statistics:</b>
</td>
<td  class="td_arrow_right">

</td>
</tr>
<tr>
<td  class="td_arrow_left">

</td>
<td  class="td_pblock_left">

</td>
<td  class="td_sym_center">

</td>
<td  class="td_pblock_right">
wr_transmission_rx_stat7_rx_latency_acc_cnt_i[31:0]
</td>
<td  class="td_arrow_right">
&lArr;
</td>
</tr>
<tr>
<td  class="td_arrow_left">

</td>
<td  class="td_pblock_left">

</td>
<td  class="td_sym_center">
&nbsp;
</td>
<td  class="td_pblock_right">

</td>
<td  class="td_arrow_right">

</td>
</tr>
<tr>
<td  class="td_arrow_left">

</td>
<td  class="td_pblock_left">

</td>
<td  class="td_sym_center">

</td>
<td  class="td_pblock_right">
<b>Rx statistics:</b>
</td>
<td  class="td_arrow_right">

</td>
</tr>
<tr>
<td  class="td_arrow_left">

</td>
<td  class="td_pblock_left">

</td>
<td  class="td_sym_center">

</td>
<td  class="td_pblock_right">
wr_transmission_rx_stat8_rx_lost_block_cnt_i[31:0]
</td>
<td  class="td_arrow_right">
&lArr;
</td>
</tr>
<tr>
<td  class="td_arrow_left">

</td>
<td  class="td_pblock_left">

</td>
<td  class="td_sym_center">
&nbsp;
</td>
<td  class="td_pblock_right">

</td>
<td  class="td_arrow_right">

</td>
</tr>
<tr>
<td  class="td_arrow_left">

</td>
<td  class="td_pblock_left">

</td>
<td  class="td_sym_center">

</td>
<td  class="td_pblock_right">
<b>Tx Config Reg 0:</b>
</td>
<td  class="td_arrow_right">

</td>
</tr>
<tr>
<td  class="td_arrow_left">

</td>
<td  class="td_pblock_left">

</td>
<td  class="td_sym_center">

</td>
<td  class="td_pblock_right">
wr_transmission_tx_cfg0_ethertype_o[15:0]
</td>
<td  class="td_arrow_right">
&rArr;
</td>
</tr>
<tr>
<td  class="td_arrow_left">

</td>
<td  class="td_pblock_left">

</td>
<td  class="td_sym_center">
&nbsp;
</td>
<td  class="td_pblock_right">

</td>
<td  class="td_arrow_right">

</td>
</tr>
<tr>
<td  class="td_arrow_left">

</td>
<td  class="td_pblock_left">

</td>
<td  class="td_sym_center">

</td>
<td  class="td_pblock_right">
<b>Tx Config Reg 1:</b>
</td>
<td  class="td_arrow_right">

</td>
</tr>
<tr>
<td  class="td_arrow_left">

</td>
<td  class="td_pblock_left">

</td>
<td  class="td_sym_center">

</td>
<td  class="td_pblock_right">
wr_transmission_tx_cfg1_mac_local_lsb_o[31:0]
</td>
<td  class="td_arrow_right">
&rArr;
</td>
</tr>
<tr>
<td  class="td_arrow_left">

</td>
<td  class="td_pblock_left">

</td>
<td  class="td_sym_center">
&nbsp;
</td>
<td  class="td_pblock_right">

</td>
<td  class="td_arrow_right">

</td>
</tr>
<tr>
<td  class="td_arrow_left">

</td>
<td  class="td_pblock_left">

</td>
<td  class="td_sym_center">

</td>
<td  class="td_pblock_right">
<b>Tx Config Reg 2:</b>
</td>
<td  class="td_arrow_right">

</td>
</tr>
<tr>
<td  class="td_arrow_left">

</td>
<td  class="td_pblock_left">

</td>
<td  class="td_sym_center">

</td>
<td  class="td_pblock_right">
wr_transmission_tx_cfg2_mac_local_msb_o[15:0]
</td>
<td  class="td_arrow_right">
&rArr;
</td>
</tr>
<tr>
<td  class="td_arrow_left">

</td>
<td  class="td_pblock_left">

</td>
<td  class="td_sym_center">
&nbsp;
</td>
<td  class="td_pblock_right">

</td>
<td  class="td_arrow_right">

</td>
</tr>
<tr>
<td  class="td_arrow_left">

</td>
<td  class="td_pblock_left">

</td>
<td  class="td_sym_center">

</td>
<td  class="td_pblock_right">
<b>Tx Config Reg 3:</b>
</td>
<td  class="td_arrow_right">

</td>
</tr>
<tr>
<td  class="td_arrow_left">

</td>
<td  class="td_pblock_left">

</td>
<td  class="td_sym_center">

</td>
<td  class="td_pblock_right">
wr_transmission_tx_cfg3_mac_target_lsb_o[31:0]
</td>
<td  class="td_arrow_right">
&rArr;
</td>
</tr>
<tr>
<td  class="td_arrow_left">

</td>
<td  class="td_pblock_left">

</td>
<td  class="td_sym_center">
&nbsp;
</td>
<td  class="td_pblock_right">

</td>
<td  class="td_arrow_right">

</td>
</tr>
<tr>
<td  class="td_arrow_left">

</td>
<td  class="td_pblock_left">

</td>
<td  class="td_sym_center">

</td>
<td  class="td_pblock_right">
<b>Tx Config Reg 4:</b>
</td>
<td  class="td_arrow_right">

</td>
</tr>
<tr>
<td  class="td_arrow_left">

</td>
<td  class="td_pblock_left">

</td>
<td  class="td_sym_center">

</td>
<td  class="td_pblock_right">
wr_transmission_tx_cfg4_mac_target_msb_o[15:0]
</td>
<td  class="td_arrow_right">
&rArr;
</td>
</tr>
<tr>
<td  class="td_arrow_left">

</td>
<td  class="td_pblock_left">

</td>
<td  class="td_sym_center">
&nbsp;
</td>
<td  class="td_pblock_right">

</td>
<td  class="td_arrow_right">

</td>
</tr>
<tr>
<td  class="td_arrow_left">

</td>
<td  class="td_pblock_left">

</td>
<td  class="td_sym_center">

</td>
<td  class="td_pblock_right">
<b>Rx Config Reg 0:</b>
</td>
<td  class="td_arrow_right">

</td>
</tr>
<tr>
<td  class="td_arrow_left">

</td>
<td  class="td_pblock_left">

</td>
<td  class="td_sym_center">

</td>
<td  class="td_pblock_right">
wr_transmission_rx_cfg0_ethertype_o[15:0]
</td>
<td  class="td_arrow_right">
&rArr;
</td>
</tr>
<tr>
<td  class="td_arrow_left">

</td>
<td  class="td_pblock_left">

</td>
<td  class="td_sym_center">

</td>
<td  class="td_pblock_right">
wr_transmission_rx_cfg0_accept_broadcast_o
</td>
<td  class="td_arrow_right">
&rarr;
</td>
</tr>
<tr>
<td  class="td_arrow_left">

</td>
<td  class="td_pblock_left">

</td>
<td  class="td_sym_center">

</td>
<td  class="td_pblock_right">
wr_transmission_rx_cfg0_filter_remote_o
</td>
<td  class="td_arrow_right">
&rarr;
</td>
</tr>
<tr>
<td  class="td_arrow_left">

</td>
<td  class="td_pblock_left">

</td>
<td  class="td_sym_center">
&nbsp;
</td>
<td  class="td_pblock_right">

</td>
<td  class="td_arrow_right">

</td>
</tr>
<tr>
<td  class="td_arrow_left">

</td>
<td  class="td_pblock_left">

</td>
<td  class="td_sym_center">

</td>
<td  class="td_pblock_right">
<b>Rx Config Reg 1:</b>
</td>
<td  class="td_arrow_right">

</td>
</tr>
<tr>
<td  class="td_arrow_left">

</td>
<td  class="td_pblock_left">

</td>
<td  class="td_sym_center">

</td>
<td  class="td_pblock_right">
wr_transmission_rx_cfg1_mac_local_lsb_o[31:0]
</td>
<td  class="td_arrow_right">
&rArr;
</td>
</tr>
<tr>
<td  class="td_arrow_left">

</td>
<td  class="td_pblock_left">

</td>
<td  class="td_sym_center">
&nbsp;
</td>
<td  class="td_pblock_right">

</td>
<td  class="td_arrow_right">

</td>
</tr>
<tr>
<td  class="td_arrow_left">

</td>
<td  class="td_pblock_left">

</td>
<td  class="td_sym_center">

</td>
<td  class="td_pblock_right">
<b>Rx Config Reg 2:</b>
</td>
<td  class="td_arrow_right">

</td>
</tr>
<tr>
<td  class="td_arrow_left">

</td>
<td  class="td_pblock_left">

</td>
<td  class="td_sym_center">

</td>
<td  class="td_pblock_right">
wr_transmission_rx_cfg2_mac_local_msb_o[15:0]
</td>
<td  class="td_arrow_right">
&rArr;
</td>
</tr>
<tr>
<td  class="td_arrow_left">

</td>
<td  class="td_pblock_left">

</td>
<td  class="td_sym_center">
&nbsp;
</td>
<td  class="td_pblock_right">

</td>
<td  class="td_arrow_right">

</td>
</tr>
<tr>
<td  class="td_arrow_left">

</td>
<td  class="td_pblock_left">

</td>
<td  class="td_sym_center">

</td>
<td  class="td_pblock_right">
<b>Rx Config Reg 3:</b>
</td>
<td  class="td_arrow_right">

</td>
</tr>
<tr>
<td  class="td_arrow_left">

</td>
<td  class="td_pblock_left">

</td>
<td  class="td_sym_center">

</td>
<td  class="td_pblock_right">
wr_transmission_rx_cfg3_mac_remote_lsb_o[31:0]
</td>
<td  class="td_arrow_right">
&rArr;
</td>
</tr>
<tr>
<td  class="td_arrow_left">

</td>
<td  class="td_pblock_left">

</td>
<td  class="td_sym_center">
&nbsp;
</td>
<td  class="td_pblock_right">

</td>
<td  class="td_arrow_right">

</td>
</tr>
<tr>
<td  class="td_arrow_left">

</td>
<td  class="td_pblock_left">

</td>
<td  class="td_sym_center">

</td>
<td  class="td_pblock_right">
<b>Rx Config Reg 4:</b>
</td>
<td  class="td_arrow_right">

</td>
</tr>
<tr>
<td  class="td_arrow_left">

</td>
<td  class="td_pblock_left">

</td>
<td  class="td_sym_center">

</td>
<td  class="td_pblock_right">
wr_transmission_rx_cfg4_mac_remote_msb_o[15:0]
</td>
<td  class="td_arrow_right">
&rArr;
</td>
</tr>
<tr>
<td  class="td_arrow_left">

</td>
<td  class="td_pblock_left">

</td>
<td  class="td_sym_center">
&nbsp;
</td>
<td  class="td_pblock_right">

</td>
<td  class="td_arrow_right">

</td>
</tr>
<tr>
<td  class="td_arrow_left">

</td>
<td  class="td_pblock_left">

</td>
<td  class="td_sym_center">

</td>
<td  class="td_pblock_right">
<b>Rx Config Reg 5:</b>
</td>
<td  class="td_arrow_right">

</td>
</tr>
<tr>
<td  class="td_arrow_left">

</td>
<td  class="td_pblock_left">

</td>
<td  class="td_sym_center">

</td>
<td  class="td_pblock_right">
wr_transmission_rx_cfg5_fixed_latency_o[27:0]
</td>
<td  class="td_arrow_right">
&rArr;
</td>
</tr>
<tr>
<td  class="td_arrow_left">

</td>
<td  class="td_pblock_left">

</td>
<td  class="td_sym_center">
&nbsp;
</td>
<td  class="td_pblock_right">

</td>
<td  class="td_arrow_right">

</td>
</tr>
<tr>
<td  class="td_arrow_left">

</td>
<td  class="td_pblock_left">

</td>
<td  class="td_sym_center">

</td>
<td  class="td_pblock_right">
<b>TxRx Config Override:</b>
</td>
<td  class="td_arrow_right">

</td>
</tr>
<tr>
<td  class="td_arrow_left">

</td>
<td  class="td_pblock_left">

</td>
<td  class="td_sym_center">

</td>
<td  class="td_pblock_right">
wr_transmission_cfg_or_tx_ethtype_o
</td>
<td  class="td_arrow_right">
&rarr;
</td>
</tr>
<tr>
<td  class="td_arrow_left">

</td>
<td  class="td_pblock_left">

</td>
<td  class="td_sym_center">

</td>
<td  class="td_pblock_right">
wr_transmission_cfg_or_tx_mac_loc_o
</td>
<td  class="td_arrow_right">
&rarr;
</td>
</tr>
<tr>
<td  class="td_arrow_left">

</td>
<td  class="td_pblock_left">

</td>
<td  class="td_sym_center">

</td>
<td  class="td_pblock_right">
wr_transmission_cfg_or_tx_mac_tar_o
</td>
<td  class="td_arrow_right">
&rarr;
</td>
</tr>
<tr>
<td  class="td_arrow_left">

</td>
<td  class="td_pblock_left">

</td>
<td  class="td_sym_center">

</td>
<td  class="td_pblock_right">
wr_transmission_cfg_or_rx_ethertype_o
</td>
<td  class="td_arrow_right">
&rarr;
</td>
</tr>
<tr>
<td  class="td_arrow_left">

</td>
<td  class="td_pblock_left">

</td>
<td  class="td_sym_center">

</td>
<td  class="td_pblock_right">
wr_transmission_cfg_or_rx_mac_loc_o
</td>
<td  class="td_arrow_right">
&rarr;
</td>
</tr>
<tr>
<td  class="td_arrow_left">

</td>
<td  class="td_pblock_left">

</td>
<td  class="td_sym_center">

</td>
<td  class="td_pblock_right">
wr_transmission_cfg_or_rx_mac_rem_o
</td>
<td  class="td_arrow_right">
&rarr;
</td>
</tr>
<tr>
<td  class="td_arrow_left">

</td>
<td  class="td_pblock_left">

</td>
<td  class="td_sym_center">

</td>
<td  class="td_pblock_right">
wr_transmission_cfg_or_rx_acc_broadcast_o
</td>
<td  class="td_arrow_right">
&rarr;
</td>
</tr>
<tr>
<td  class="td_arrow_left">

</td>
<td  class="td_pblock_left">

</td>
<td  class="td_sym_center">

</td>
<td  class="td_pblock_right">
wr_transmission_cfg_or_rx_ftr_remote_o
</td>
<td  class="td_arrow_right">
&rarr;
</td>
</tr>
<tr>
<td  class="td_arrow_left">

</td>
<td  class="td_pblock_left">

</td>
<td  class="td_sym_center">

</td>
<td  class="td_pblock_right">
wr_transmission_cfg_or_rx_fix_lat_o
</td>
<td  class="td_arrow_right">
&rarr;
</td>
</tr>
<tr>
<td  class="td_arrow_left">

</td>
<td  class="td_pblock_left">

</td>
<td  class="td_sym_center">
&nbsp;
</td>
<td  class="td_pblock_right">

</td>
<td  class="td_arrow_right">

</td>
</tr>
<tr>
<td  class="td_arrow_left">

</td>
<td  class="td_pblock_left">

</td>
<td  class="td_sym_center">

</td>
<td  class="td_pblock_right">
<b>DBG Control register:</b>
</td>
<td  class="td_arrow_right">

</td>
</tr>
<tr>
<td  class="td_arrow_left">

</td>
<td  class="td_pblock_left">

</td>
<td  class="td_sym_center">

</td>
<td  class="td_pblock_right">
wr_transmission_dbg_ctrl_mux_o
</td>
<td  class="td_arrow_right">
&rarr;
</td>
</tr>
<tr>
<td  class="td_arrow_left">

</td>
<td  class="td_pblock_left">

</td>
<td  class="td_sym_center">

</td>
<td  class="td_pblock_right">
wr_transmission_dbg_ctrl_start_byte_o[7:0]
</td>
<td  class="td_arrow_right">
&rArr;
</td>
</tr>
<tr>
<td  class="td_arrow_left">

</td>
<td  class="td_pblock_left">

</td>
<td  class="td_sym_center">
&nbsp;
</td>
<td  class="td_pblock_right">

</td>
<td  class="td_arrow_right">

</td>
</tr>
<tr>
<td  class="td_arrow_left">

</td>
<td  class="td_pblock_left">

</td>
<td  class="td_sym_center">

</td>
<td  class="td_pblock_right">
<b>DBG Data:</b>
</td>
<td  class="td_arrow_right">

</td>
</tr>
<tr>
<td  class="td_arrow_left">

</td>
<td  class="td_pblock_left">

</td>
<td  class="td_sym_center">

</td>
<td  class="td_pblock_right">
wr_transmission_dbg_data_i[31:0]
</td>
<td  class="td_arrow_right">
&lArr;
</td>
</tr>
<tr>
<td  class="td_arrow_left">

</td>
<td  class="td_pblock_left">

</td>
<td  class="td_sym_center">
&nbsp;
</td>
<td  class="td_pblock_right">

</td>
<td  class="td_arrow_right">

</td>
</tr>
<tr>
<td  class="td_arrow_left">

</td>
<td  class="td_pblock_left">

</td>
<td  class="td_sym_center">

</td>
<td  class="td_pblock_right">
<b>DBG RX_BVALUE:</b>
</td>
<td  class="td_arrow_right">

</td>
</tr>
<tr>
<td  class="td_arrow_left">

</td>
<td  class="td_pblock_left">

</td>
<td  class="td_sym_center">

</td>
<td  class="td_pblock_right">
wr_transmission_dbg_rx_bvalue_i[31:0]
</td>
<td  class="td_arrow_right">
&lArr;
</td>
</tr>
<tr>
<td  class="td_arrow_left">

</td>
<td  class="td_pblock_left">

</td>
<td  class="td_sym_center">
&nbsp;
</td>
<td  class="td_pblock_right">

</td>
<td  class="td_arrow_right">

</td>
</tr>
<tr>
<td  class="td_arrow_left">

</td>
<td  class="td_pblock_left">

</td>
<td  class="td_sym_center">

</td>
<td  class="td_pblock_right">
<b>DBG tx bvalue:</b>
</td>
<td  class="td_arrow_right">

</td>
</tr>
<tr>
<td  class="td_arrow_left">

</td>
<td  class="td_pblock_left">

</td>
<td  class="td_sym_center">

</td>
<td  class="td_pblock_right">
wr_transmission_dbg_tx_bvalue_i[31:0]
</td>
<td  class="td_arrow_right">
&lArr;
</td>
</tr>
<tr>
<td  class="td_arrow_left">

</td>
<td  class="td_pblock_left">

</td>
<td  class="td_sym_center">
&nbsp;
</td>
<td  class="td_pblock_right">

</td>
<td  class="td_arrow_right">

</td>
</tr>
<tr>
<td  class="td_arrow_left">

</td>
<td  class="td_pblock_left">

</td>
<td  class="td_sym_center">

</td>
<td  class="td_pblock_right">
<b>Test value:</b>
</td>
<td  class="td_arrow_right">

</td>
</tr>
<tr>
<td  class="td_arrow_left">

</td>
<td  class="td_pblock_left">

</td>
<td  class="td_sym_center">

</td>
<td  class="td_pblock_right">
wr_transmission_dummy_dummy_i[31:0]
</td>
<td  class="td_arrow_right">
&lArr;
</td>
</tr>
</table>

<h3><a name="sect_3_0">3. Register description</a></h3>
<a name="SSCR1"></a>
<h3><a name="sect_3_1">3.1. Statistics status and ctrl register</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td  class="td_code">
wr_transmission_sscr1
</td>
</tr>
<tr>
<td >
<b>HW address: </b>
</td>
<td  class="td_code">
0x0
</td>
</tr>
<tr>
<td >
<b>C prefix: </b>
</td>
<td  class="td_code">
SSCR1
</td>
</tr>
<tr>
<td >
<b>C offset: </b>
</td>
<td  class="td_code">
0x0
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td  class="td_bit">
31
</td>
<td  class="td_bit">
30
</td>
<td  class="td_bit">
29
</td>
<td  class="td_bit">
28
</td>
<td  class="td_bit">
27
</td>
<td  class="td_bit">
26
</td>
<td  class="td_bit">
25
</td>
<td  class="td_bit">
24
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8  class="td_field">
RST_TS_CYC[27:20]
</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td  class="td_bit">
23
</td>
<td  class="td_bit">
22
</td>
<td  class="td_bit">
21
</td>
<td  class="td_bit">
20
</td>
<td  class="td_bit">
19
</td>
<td  class="td_bit">
18
</td>
<td  class="td_bit">
17
</td>
<td  class="td_bit">
16
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8  class="td_field">
RST_TS_CYC[19:12]
</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td  class="td_bit">
15
</td>
<td  class="td_bit">
14
</td>
<td  class="td_bit">
13
</td>
<td  class="td_bit">
12
</td>
<td  class="td_bit">
11
</td>
<td  class="td_bit">
10
</td>
<td  class="td_bit">
9
</td>
<td  class="td_bit">
8
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8  class="td_field">
RST_TS_CYC[11:4]
</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td  class="td_bit">
7
</td>
<td  class="td_bit">
6
</td>
<td  class="td_bit">
5
</td>
<td  class="td_bit">
4
</td>
<td  class="td_bit">
3
</td>
<td  class="td_bit">
2
</td>
<td  class="td_bit">
1
</td>
<td  class="td_bit">
0
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=4  class="td_field">
RST_TS_CYC[3:0]
</td>
<td style="border: solid 1px black;" colspan=1  class="td_field">
RX_LATENCY_ACC_OVERFLOW
</td>
<td style="border: solid 1px black;" colspan=1  class="td_field">
SNAPSHOT_STATS
</td>
<td style="border: solid 1px black;" colspan=1  class="td_field">
RST_SEQ_ID
</td>
<td style="border: solid 1px black;" colspan=1  class="td_field">
RST_STATS
</td>
<td >

</td>
<td >

</td>
<td >

</td>
</tr>
</table>
<ul>
<li><b>
RST_STATS
</b>[<i>write-only</i>]: Reset statistics
<br>Writing 1 reset counters, latency acc/max/min. This reset is timestamped
<li><b>
RST_SEQ_ID
</b>[<i>write-only</i>]: Reset tx seq id
<br>Writing 1 reset sequence ID of transmitted frames
<li><b>
SNAPSHOT_STATS
</b>[<i>read/write</i>]: Snapshot statistics
<br>Writing 1 snapshots statistics for reading, it means that all the counters <br>                    are copied at the same instant to registers and this registers can be read<br>                    via wishbone/snmp while the counters are still running in the background. <br>                    this allows to read coherent data
<li><b>
RX_LATENCY_ACC_OVERFLOW
</b>[<i>read-only</i>]: Latency accumulator overflow
<br>Latency accumulator overflow - the lateny accumulator value is invalid
<li><b>
RST_TS_CYC
</b>[<i>read-only</i>]: Reset timestamp cycles
<br>Timestamp of the last reset of stats (RST_STAT) -- count of clock cycles
</ul>
<a name="SSCR2"></a>
<h3><a name="sect_3_2">3.2. Statistics status and ctrl register</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td  class="td_code">
wr_transmission_sscr2
</td>
</tr>
<tr>
<td >
<b>HW address: </b>
</td>
<td  class="td_code">
0x1
</td>
</tr>
<tr>
<td >
<b>C prefix: </b>
</td>
<td  class="td_code">
SSCR2
</td>
</tr>
<tr>
<td >
<b>C offset: </b>
</td>
<td  class="td_code">
0x4
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td  class="td_bit">
31
</td>
<td  class="td_bit">
30
</td>
<td  class="td_bit">
29
</td>
<td  class="td_bit">
28
</td>
<td  class="td_bit">
27
</td>
<td  class="td_bit">
26
</td>
<td  class="td_bit">
25
</td>
<td  class="td_bit">
24
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8  class="td_field">
RST_TS_TAI_LSB[31:24]
</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td  class="td_bit">
23
</td>
<td  class="td_bit">
22
</td>
<td  class="td_bit">
21
</td>
<td  class="td_bit">
20
</td>
<td  class="td_bit">
19
</td>
<td  class="td_bit">
18
</td>
<td  class="td_bit">
17
</td>
<td  class="td_bit">
16
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8  class="td_field">
RST_TS_TAI_LSB[23:16]
</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td  class="td_bit">
15
</td>
<td  class="td_bit">
14
</td>
<td  class="td_bit">
13
</td>
<td  class="td_bit">
12
</td>
<td  class="td_bit">
11
</td>
<td  class="td_bit">
10
</td>
<td  class="td_bit">
9
</td>
<td  class="td_bit">
8
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8  class="td_field">
RST_TS_TAI_LSB[15:8]
</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td  class="td_bit">
7
</td>
<td  class="td_bit">
6
</td>
<td  class="td_bit">
5
</td>
<td  class="td_bit">
4
</td>
<td  class="td_bit">
3
</td>
<td  class="td_bit">
2
</td>
<td  class="td_bit">
1
</td>
<td  class="td_bit">
0
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8  class="td_field">
RST_TS_TAI_LSB[7:0]
</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
</tr>
</table>
<ul>
<li><b>
RST_TS_TAI_LSB
</b>[<i>read-only</i>]: Reset timestamp 32 LSB of TAI
<br>Timestamp of the last reset of stats (RST_STAT)  -- LSB 32 bits of TAI
</ul>
<a name="TX_STAT"></a>
<h3><a name="sect_3_3">3.3. Tx statistics</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td  class="td_code">
wr_transmission_tx_stat
</td>
</tr>
<tr>
<td >
<b>HW address: </b>
</td>
<td  class="td_code">
0x2
</td>
</tr>
<tr>
<td >
<b>C prefix: </b>
</td>
<td  class="td_code">
TX_STAT
</td>
</tr>
<tr>
<td >
<b>C offset: </b>
</td>
<td  class="td_code">
0x8
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td  class="td_bit">
31
</td>
<td  class="td_bit">
30
</td>
<td  class="td_bit">
29
</td>
<td  class="td_bit">
28
</td>
<td  class="td_bit">
27
</td>
<td  class="td_bit">
26
</td>
<td  class="td_bit">
25
</td>
<td  class="td_bit">
24
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8  class="td_field">
TX_SENT_CNT[31:24]
</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td  class="td_bit">
23
</td>
<td  class="td_bit">
22
</td>
<td  class="td_bit">
21
</td>
<td  class="td_bit">
20
</td>
<td  class="td_bit">
19
</td>
<td  class="td_bit">
18
</td>
<td  class="td_bit">
17
</td>
<td  class="td_bit">
16
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8  class="td_field">
TX_SENT_CNT[23:16]
</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td  class="td_bit">
15
</td>
<td  class="td_bit">
14
</td>
<td  class="td_bit">
13
</td>
<td  class="td_bit">
12
</td>
<td  class="td_bit">
11
</td>
<td  class="td_bit">
10
</td>
<td  class="td_bit">
9
</td>
<td  class="td_bit">
8
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8  class="td_field">
TX_SENT_CNT[15:8]
</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td  class="td_bit">
7
</td>
<td  class="td_bit">
6
</td>
<td  class="td_bit">
5
</td>
<td  class="td_bit">
4
</td>
<td  class="td_bit">
3
</td>
<td  class="td_bit">
2
</td>
<td  class="td_bit">
1
</td>
<td  class="td_bit">
0
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8  class="td_field">
TX_SENT_CNT[7:0]
</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
</tr>
</table>
<ul>
<li><b>
TX_SENT_CNT
</b>[<i>read-only</i>]: WR Streamer frame sent count
<br>Number of sent wr streamer frames since reset
</ul>
<a name="RX_STAT1"></a>
<h3><a name="sect_3_4">3.4. Rx statistics</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td  class="td_code">
wr_transmission_rx_stat1
</td>
</tr>
<tr>
<td >
<b>HW address: </b>
</td>
<td  class="td_code">
0x3
</td>
</tr>
<tr>
<td >
<b>C prefix: </b>
</td>
<td  class="td_code">
RX_STAT1
</td>
</tr>
<tr>
<td >
<b>C offset: </b>
</td>
<td  class="td_code">
0xc
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td  class="td_bit">
31
</td>
<td  class="td_bit">
30
</td>
<td  class="td_bit">
29
</td>
<td  class="td_bit">
28
</td>
<td  class="td_bit">
27
</td>
<td  class="td_bit">
26
</td>
<td  class="td_bit">
25
</td>
<td  class="td_bit">
24
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8  class="td_field">
RX_RCVD_CNT[31:24]
</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td  class="td_bit">
23
</td>
<td  class="td_bit">
22
</td>
<td  class="td_bit">
21
</td>
<td  class="td_bit">
20
</td>
<td  class="td_bit">
19
</td>
<td  class="td_bit">
18
</td>
<td  class="td_bit">
17
</td>
<td  class="td_bit">
16
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8  class="td_field">
RX_RCVD_CNT[23:16]
</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td  class="td_bit">
15
</td>
<td  class="td_bit">
14
</td>
<td  class="td_bit">
13
</td>
<td  class="td_bit">
12
</td>
<td  class="td_bit">
11
</td>
<td  class="td_bit">
10
</td>
<td  class="td_bit">
9
</td>
<td  class="td_bit">
8
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8  class="td_field">
RX_RCVD_CNT[15:8]
</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td  class="td_bit">
7
</td>
<td  class="td_bit">
6
</td>
<td  class="td_bit">
5
</td>
<td  class="td_bit">
4
</td>
<td  class="td_bit">
3
</td>
<td  class="td_bit">
2
</td>
<td  class="td_bit">
1
</td>
<td  class="td_bit">
0
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8  class="td_field">
RX_RCVD_CNT[7:0]
</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
</tr>
</table>
<ul>
<li><b>
RX_RCVD_CNT
</b>[<i>read-only</i>]: WR Streamer frame received count
<br>Number of received wr streamer frames since reset
</ul>
<a name="RX_STAT2"></a>
<h3><a name="sect_3_5">3.5. Rx statistics</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td  class="td_code">
wr_transmission_rx_stat2
</td>
</tr>
<tr>
<td >
<b>HW address: </b>
</td>
<td  class="td_code">
0x4
</td>
</tr>
<tr>
<td >
<b>C prefix: </b>
</td>
<td  class="td_code">
RX_STAT2
</td>
</tr>
<tr>
<td >
<b>C offset: </b>
</td>
<td  class="td_code">
0x10
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td  class="td_bit">
31
</td>
<td  class="td_bit">
30
</td>
<td  class="td_bit">
29
</td>
<td  class="td_bit">
28
</td>
<td  class="td_bit">
27
</td>
<td  class="td_bit">
26
</td>
<td  class="td_bit">
25
</td>
<td  class="td_bit">
24
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8  class="td_field">
RX_LOSS_CNT[31:24]
</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td  class="td_bit">
23
</td>
<td  class="td_bit">
22
</td>
<td  class="td_bit">
21
</td>
<td  class="td_bit">
20
</td>
<td  class="td_bit">
19
</td>
<td  class="td_bit">
18
</td>
<td  class="td_bit">
17
</td>
<td  class="td_bit">
16
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8  class="td_field">
RX_LOSS_CNT[23:16]
</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td  class="td_bit">
15
</td>
<td  class="td_bit">
14
</td>
<td  class="td_bit">
13
</td>
<td  class="td_bit">
12
</td>
<td  class="td_bit">
11
</td>
<td  class="td_bit">
10
</td>
<td  class="td_bit">
9
</td>
<td  class="td_bit">
8
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8  class="td_field">
RX_LOSS_CNT[15:8]
</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td  class="td_bit">
7
</td>
<td  class="td_bit">
6
</td>
<td  class="td_bit">
5
</td>
<td  class="td_bit">
4
</td>
<td  class="td_bit">
3
</td>
<td  class="td_bit">
2
</td>
<td  class="td_bit">
1
</td>
<td  class="td_bit">
0
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8  class="td_field">
RX_LOSS_CNT[7:0]
</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
</tr>
</table>
<ul>
<li><b>
RX_LOSS_CNT
</b>[<i>read-only</i>]: WR Streamer frame loss count
<br>Number of lost wr streamer frames since reset
</ul>
<a name="RX_STAT3"></a>
<h3><a name="sect_3_6">3.6. Rx statistics</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td  class="td_code">
wr_transmission_rx_stat3
</td>
</tr>
<tr>
<td >
<b>HW address: </b>
</td>
<td  class="td_code">
0x5
</td>
</tr>
<tr>
<td >
<b>C prefix: </b>
</td>
<td  class="td_code">
RX_STAT3
</td>
</tr>
<tr>
<td >
<b>C offset: </b>
</td>
<td  class="td_code">
0x14
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td  class="td_bit">
31
</td>
<td  class="td_bit">
30
</td>
<td  class="td_bit">
29
</td>
<td  class="td_bit">
28
</td>
<td  class="td_bit">
27
</td>
<td  class="td_bit">
26
</td>
<td  class="td_bit">
25
</td>
<td  class="td_bit">
24
</td>
</tr>
<tr>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td style="border: solid 1px black;" colspan=4  class="td_field">
RX_LATENCY_MAX[27:24]
</td>
<td >

</td>
<td >

</td>
<td >

</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td  class="td_bit">
23
</td>
<td  class="td_bit">
22
</td>
<td  class="td_bit">
21
</td>
<td  class="td_bit">
20
</td>
<td  class="td_bit">
19
</td>
<td  class="td_bit">
18
</td>
<td  class="td_bit">
17
</td>
<td  class="td_bit">
16
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8  class="td_field">
RX_LATENCY_MAX[23:16]
</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td  class="td_bit">
15
</td>
<td  class="td_bit">
14
</td>
<td  class="td_bit">
13
</td>
<td  class="td_bit">
12
</td>
<td  class="td_bit">
11
</td>
<td  class="td_bit">
10
</td>
<td  class="td_bit">
9
</td>
<td  class="td_bit">
8
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8  class="td_field">
RX_LATENCY_MAX[15:8]
</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td  class="td_bit">
7
</td>
<td  class="td_bit">
6
</td>
<td  class="td_bit">
5
</td>
<td  class="td_bit">
4
</td>
<td  class="td_bit">
3
</td>
<td  class="td_bit">
2
</td>
<td  class="td_bit">
1
</td>
<td  class="td_bit">
0
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8  class="td_field">
RX_LATENCY_MAX[7:0]
</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
</tr>
</table>
<ul>
<li><b>
RX_LATENCY_MAX
</b>[<i>read-only</i>]: WR Streamer frame latency
<br>Maximum latency of received frames since reset
</ul>
<a name="RX_STAT4"></a>
<h3><a name="sect_3_7">3.7. Rx statistics</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td  class="td_code">
wr_transmission_rx_stat4
</td>
</tr>
<tr>
<td >
<b>HW address: </b>
</td>
<td  class="td_code">
0x6
</td>
</tr>
<tr>
<td >
<b>C prefix: </b>
</td>
<td  class="td_code">
RX_STAT4
</td>
</tr>
<tr>
<td >
<b>C offset: </b>
</td>
<td  class="td_code">
0x18
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td  class="td_bit">
31
</td>
<td  class="td_bit">
30
</td>
<td  class="td_bit">
29
</td>
<td  class="td_bit">
28
</td>
<td  class="td_bit">
27
</td>
<td  class="td_bit">
26
</td>
<td  class="td_bit">
25
</td>
<td  class="td_bit">
24
</td>
</tr>
<tr>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td style="border: solid 1px black;" colspan=4  class="td_field">
RX_LATENCY_MIN[27:24]
</td>
<td >

</td>
<td >

</td>
<td >

</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td  class="td_bit">
23
</td>
<td  class="td_bit">
22
</td>
<td  class="td_bit">
21
</td>
<td  class="td_bit">
20
</td>
<td  class="td_bit">
19
</td>
<td  class="td_bit">
18
</td>
<td  class="td_bit">
17
</td>
<td  class="td_bit">
16
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8  class="td_field">
RX_LATENCY_MIN[23:16]
</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td  class="td_bit">
15
</td>
<td  class="td_bit">
14
</td>
<td  class="td_bit">
13
</td>
<td  class="td_bit">
12
</td>
<td  class="td_bit">
11
</td>
<td  class="td_bit">
10
</td>
<td  class="td_bit">
9
</td>
<td  class="td_bit">
8
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8  class="td_field">
RX_LATENCY_MIN[15:8]
</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td  class="td_bit">
7
</td>
<td  class="td_bit">
6
</td>
<td  class="td_bit">
5
</td>
<td  class="td_bit">
4
</td>
<td  class="td_bit">
3
</td>
<td  class="td_bit">
2
</td>
<td  class="td_bit">
1
</td>
<td  class="td_bit">
0
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8  class="td_field">
RX_LATENCY_MIN[7:0]
</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
</tr>
</table>
<ul>
<li><b>
RX_LATENCY_MIN
</b>[<i>read-only</i>]: WR Streamer frame latency
<br>Minimum latency of received frames since reset
</ul>
<a name="RX_STAT5"></a>
<h3><a name="sect_3_8">3.8. Rx statistics</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td  class="td_code">
wr_transmission_rx_stat5
</td>
</tr>
<tr>
<td >
<b>HW address: </b>
</td>
<td  class="td_code">
0x7
</td>
</tr>
<tr>
<td >
<b>C prefix: </b>
</td>
<td  class="td_code">
RX_STAT5
</td>
</tr>
<tr>
<td >
<b>C offset: </b>
</td>
<td  class="td_code">
0x1c
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td  class="td_bit">
31
</td>
<td  class="td_bit">
30
</td>
<td  class="td_bit">
29
</td>
<td  class="td_bit">
28
</td>
<td  class="td_bit">
27
</td>
<td  class="td_bit">
26
</td>
<td  class="td_bit">
25
</td>
<td  class="td_bit">
24
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8  class="td_field">
RX_LATENCY_ACC_LSB[31:24]
</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td  class="td_bit">
23
</td>
<td  class="td_bit">
22
</td>
<td  class="td_bit">
21
</td>
<td  class="td_bit">
20
</td>
<td  class="td_bit">
19
</td>
<td  class="td_bit">
18
</td>
<td  class="td_bit">
17
</td>
<td  class="td_bit">
16
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8  class="td_field">
RX_LATENCY_ACC_LSB[23:16]
</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td  class="td_bit">
15
</td>
<td  class="td_bit">
14
</td>
<td  class="td_bit">
13
</td>
<td  class="td_bit">
12
</td>
<td  class="td_bit">
11
</td>
<td  class="td_bit">
10
</td>
<td  class="td_bit">
9
</td>
<td  class="td_bit">
8
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8  class="td_field">
RX_LATENCY_ACC_LSB[15:8]
</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td  class="td_bit">
7
</td>
<td  class="td_bit">
6
</td>
<td  class="td_bit">
5
</td>
<td  class="td_bit">
4
</td>
<td  class="td_bit">
3
</td>
<td  class="td_bit">
2
</td>
<td  class="td_bit">
1
</td>
<td  class="td_bit">
0
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8  class="td_field">
RX_LATENCY_ACC_LSB[7:0]
</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
</tr>
</table>
<ul>
<li><b>
RX_LATENCY_ACC_LSB
</b>[<i>read-only</i>]: WR Streamer frame latency
<br>Accumulated latency (LSB) of received frames since reset
</ul>
<a name="RX_STAT6"></a>
<h3><a name="sect_3_9">3.9. Rx statistics</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td  class="td_code">
wr_transmission_rx_stat6
</td>
</tr>
<tr>
<td >
<b>HW address: </b>
</td>
<td  class="td_code">
0x8
</td>
</tr>
<tr>
<td >
<b>C prefix: </b>
</td>
<td  class="td_code">
RX_STAT6
</td>
</tr>
<tr>
<td >
<b>C offset: </b>
</td>
<td  class="td_code">
0x20
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td  class="td_bit">
31
</td>
<td  class="td_bit">
30
</td>
<td  class="td_bit">
29
</td>
<td  class="td_bit">
28
</td>
<td  class="td_bit">
27
</td>
<td  class="td_bit">
26
</td>
<td  class="td_bit">
25
</td>
<td  class="td_bit">
24
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8  class="td_field">
RX_LATENCY_ACC_MSB[31:24]
</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td  class="td_bit">
23
</td>
<td  class="td_bit">
22
</td>
<td  class="td_bit">
21
</td>
<td  class="td_bit">
20
</td>
<td  class="td_bit">
19
</td>
<td  class="td_bit">
18
</td>
<td  class="td_bit">
17
</td>
<td  class="td_bit">
16
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8  class="td_field">
RX_LATENCY_ACC_MSB[23:16]
</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td  class="td_bit">
15
</td>
<td  class="td_bit">
14
</td>
<td  class="td_bit">
13
</td>
<td  class="td_bit">
12
</td>
<td  class="td_bit">
11
</td>
<td  class="td_bit">
10
</td>
<td  class="td_bit">
9
</td>
<td  class="td_bit">
8
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8  class="td_field">
RX_LATENCY_ACC_MSB[15:8]
</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td  class="td_bit">
7
</td>
<td  class="td_bit">
6
</td>
<td  class="td_bit">
5
</td>
<td  class="td_bit">
4
</td>
<td  class="td_bit">
3
</td>
<td  class="td_bit">
2
</td>
<td  class="td_bit">
1
</td>
<td  class="td_bit">
0
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8  class="td_field">
RX_LATENCY_ACC_MSB[7:0]
</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
</tr>
</table>
<ul>
<li><b>
RX_LATENCY_ACC_MSB
</b>[<i>read-only</i>]: WR Streamer frame latency
<br>Accumulated latency (MSB) of received frames since reset
</ul>
<a name="RX_STAT7"></a>
<h3><a name="sect_3_10">3.10. Rx statistics</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td  class="td_code">
wr_transmission_rx_stat7
</td>
</tr>
<tr>
<td >
<b>HW address: </b>
</td>
<td  class="td_code">
0x9
</td>
</tr>
<tr>
<td >
<b>C prefix: </b>
</td>
<td  class="td_code">
RX_STAT7
</td>
</tr>
<tr>
<td >
<b>C offset: </b>
</td>
<td  class="td_code">
0x24
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td  class="td_bit">
31
</td>
<td  class="td_bit">
30
</td>
<td  class="td_bit">
29
</td>
<td  class="td_bit">
28
</td>
<td  class="td_bit">
27
</td>
<td  class="td_bit">
26
</td>
<td  class="td_bit">
25
</td>
<td  class="td_bit">
24
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8  class="td_field">
RX_LATENCY_ACC_CNT[31:24]
</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td  class="td_bit">
23
</td>
<td  class="td_bit">
22
</td>
<td  class="td_bit">
21
</td>
<td  class="td_bit">
20
</td>
<td  class="td_bit">
19
</td>
<td  class="td_bit">
18
</td>
<td  class="td_bit">
17
</td>
<td  class="td_bit">
16
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8  class="td_field">
RX_LATENCY_ACC_CNT[23:16]
</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td  class="td_bit">
15
</td>
<td  class="td_bit">
14
</td>
<td  class="td_bit">
13
</td>
<td  class="td_bit">
12
</td>
<td  class="td_bit">
11
</td>
<td  class="td_bit">
10
</td>
<td  class="td_bit">
9
</td>
<td  class="td_bit">
8
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8  class="td_field">
RX_LATENCY_ACC_CNT[15:8]
</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td  class="td_bit">
7
</td>
<td  class="td_bit">
6
</td>
<td  class="td_bit">
5
</td>
<td  class="td_bit">
4
</td>
<td  class="td_bit">
3
</td>
<td  class="td_bit">
2
</td>
<td  class="td_bit">
1
</td>
<td  class="td_bit">
0
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8  class="td_field">
RX_LATENCY_ACC_CNT[7:0]
</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
</tr>
</table>
<ul>
<li><b>
RX_LATENCY_ACC_CNT
</b>[<i>read-only</i>]: WR Streamer frame latency counter
<br>Counter of the accumulated frequency (so avg can be calculated in SW) since reset
</ul>
<a name="RX_STAT8"></a>
<h3><a name="sect_3_11">3.11. Rx statistics</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td  class="td_code">
wr_transmission_rx_stat8
</td>
</tr>
<tr>
<td >
<b>HW address: </b>
</td>
<td  class="td_code">
0xa
</td>
</tr>
<tr>
<td >
<b>C prefix: </b>
</td>
<td  class="td_code">
RX_STAT8
</td>
</tr>
<tr>
<td >
<b>C offset: </b>
</td>
<td  class="td_code">
0x28
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td  class="td_bit">
31
</td>
<td  class="td_bit">
30
</td>
<td  class="td_bit">
29
</td>
<td  class="td_bit">
28
</td>
<td  class="td_bit">
27
</td>
<td  class="td_bit">
26
</td>
<td  class="td_bit">
25
</td>
<td  class="td_bit">
24
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8  class="td_field">
RX_LOST_BLOCK_CNT[31:24]
</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td  class="td_bit">
23
</td>
<td  class="td_bit">
22
</td>
<td  class="td_bit">
21
</td>
<td  class="td_bit">
20
</td>
<td  class="td_bit">
19
</td>
<td  class="td_bit">
18
</td>
<td  class="td_bit">
17
</td>
<td  class="td_bit">
16
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8  class="td_field">
RX_LOST_BLOCK_CNT[23:16]
</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td  class="td_bit">
15
</td>
<td  class="td_bit">
14
</td>
<td  class="td_bit">
13
</td>
<td  class="td_bit">
12
</td>
<td  class="td_bit">
11
</td>
<td  class="td_bit">
10
</td>
<td  class="td_bit">
9
</td>
<td  class="td_bit">
8
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8  class="td_field">
RX_LOST_BLOCK_CNT[15:8]
</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td  class="td_bit">
7
</td>
<td  class="td_bit">
6
</td>
<td  class="td_bit">
5
</td>
<td  class="td_bit">
4
</td>
<td  class="td_bit">
3
</td>
<td  class="td_bit">
2
</td>
<td  class="td_bit">
1
</td>
<td  class="td_bit">
0
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8  class="td_field">
RX_LOST_BLOCK_CNT[7:0]
</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
</tr>
</table>
<ul>
<li><b>
RX_LOST_BLOCK_CNT
</b>[<i>read-only</i>]: WR Streamer block loss count
<br>Number of indications that one or more blocks in a frame were lost (probably CRC<br>                     error) since reset
</ul>
<a name="TX_CFG0"></a>
<h3><a name="sect_3_12">3.12. Tx Config Reg 0</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td  class="td_code">
wr_transmission_tx_cfg0
</td>
</tr>
<tr>
<td >
<b>HW address: </b>
</td>
<td  class="td_code">
0xb
</td>
</tr>
<tr>
<td >
<b>C prefix: </b>
</td>
<td  class="td_code">
TX_CFG0
</td>
</tr>
<tr>
<td >
<b>C offset: </b>
</td>
<td  class="td_code">
0x2c
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td  class="td_bit">
31
</td>
<td  class="td_bit">
30
</td>
<td  class="td_bit">
29
</td>
<td  class="td_bit">
28
</td>
<td  class="td_bit">
27
</td>
<td  class="td_bit">
26
</td>
<td  class="td_bit">
25
</td>
<td  class="td_bit">
24
</td>
</tr>
<tr>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td  class="td_bit">
23
</td>
<td  class="td_bit">
22
</td>
<td  class="td_bit">
21
</td>
<td  class="td_bit">
20
</td>
<td  class="td_bit">
19
</td>
<td  class="td_bit">
18
</td>
<td  class="td_bit">
17
</td>
<td  class="td_bit">
16
</td>
</tr>
<tr>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td  class="td_bit">
15
</td>
<td  class="td_bit">
14
</td>
<td  class="td_bit">
13
</td>
<td  class="td_bit">
12
</td>
<td  class="td_bit">
11
</td>
<td  class="td_bit">
10
</td>
<td  class="td_bit">
9
</td>
<td  class="td_bit">
8
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8  class="td_field">
ETHERTYPE[15:8]
</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td  class="td_bit">
7
</td>
<td  class="td_bit">
6
</td>
<td  class="td_bit">
5
</td>
<td  class="td_bit">
4
</td>
<td  class="td_bit">
3
</td>
<td  class="td_bit">
2
</td>
<td  class="td_bit">
1
</td>
<td  class="td_bit">
0
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8  class="td_field">
ETHERTYPE[7:0]
</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
</tr>
</table>
<ul>
<li><b>
ETHERTYPE
</b>[<i>read/write</i>]: Ethertype
</ul>
<a name="TX_CFG1"></a>
<h3><a name="sect_3_13">3.13. Tx Config Reg 1</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td  class="td_code">
wr_transmission_tx_cfg1
</td>
</tr>
<tr>
<td >
<b>HW address: </b>
</td>
<td  class="td_code">
0xc
</td>
</tr>
<tr>
<td >
<b>C prefix: </b>
</td>
<td  class="td_code">
TX_CFG1
</td>
</tr>
<tr>
<td >
<b>C offset: </b>
</td>
<td  class="td_code">
0x30
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td  class="td_bit">
31
</td>
<td  class="td_bit">
30
</td>
<td  class="td_bit">
29
</td>
<td  class="td_bit">
28
</td>
<td  class="td_bit">
27
</td>
<td  class="td_bit">
26
</td>
<td  class="td_bit">
25
</td>
<td  class="td_bit">
24
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8  class="td_field">
MAC_LOCAL_LSB[31:24]
</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td  class="td_bit">
23
</td>
<td  class="td_bit">
22
</td>
<td  class="td_bit">
21
</td>
<td  class="td_bit">
20
</td>
<td  class="td_bit">
19
</td>
<td  class="td_bit">
18
</td>
<td  class="td_bit">
17
</td>
<td  class="td_bit">
16
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8  class="td_field">
MAC_LOCAL_LSB[23:16]
</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td  class="td_bit">
15
</td>
<td  class="td_bit">
14
</td>
<td  class="td_bit">
13
</td>
<td  class="td_bit">
12
</td>
<td  class="td_bit">
11
</td>
<td  class="td_bit">
10
</td>
<td  class="td_bit">
9
</td>
<td  class="td_bit">
8
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8  class="td_field">
MAC_LOCAL_LSB[15:8]
</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td  class="td_bit">
7
</td>
<td  class="td_bit">
6
</td>
<td  class="td_bit">
5
</td>
<td  class="td_bit">
4
</td>
<td  class="td_bit">
3
</td>
<td  class="td_bit">
2
</td>
<td  class="td_bit">
1
</td>
<td  class="td_bit">
0
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8  class="td_field">
MAC_LOCAL_LSB[7:0]
</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
</tr>
</table>
<ul>
<li><b>
MAC_LOCAL_LSB
</b>[<i>read/write</i>]: MAC Local LSB
</ul>
<a name="TX_CFG2"></a>
<h3><a name="sect_3_14">3.14. Tx Config Reg 2</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td  class="td_code">
wr_transmission_tx_cfg2
</td>
</tr>
<tr>
<td >
<b>HW address: </b>
</td>
<td  class="td_code">
0xd
</td>
</tr>
<tr>
<td >
<b>C prefix: </b>
</td>
<td  class="td_code">
TX_CFG2
</td>
</tr>
<tr>
<td >
<b>C offset: </b>
</td>
<td  class="td_code">
0x34
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td  class="td_bit">
31
</td>
<td  class="td_bit">
30
</td>
<td  class="td_bit">
29
</td>
<td  class="td_bit">
28
</td>
<td  class="td_bit">
27
</td>
<td  class="td_bit">
26
</td>
<td  class="td_bit">
25
</td>
<td  class="td_bit">
24
</td>
</tr>
<tr>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td  class="td_bit">
23
</td>
<td  class="td_bit">
22
</td>
<td  class="td_bit">
21
</td>
<td  class="td_bit">
20
</td>
<td  class="td_bit">
19
</td>
<td  class="td_bit">
18
</td>
<td  class="td_bit">
17
</td>
<td  class="td_bit">
16
</td>
</tr>
<tr>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td  class="td_bit">
15
</td>
<td  class="td_bit">
14
</td>
<td  class="td_bit">
13
</td>
<td  class="td_bit">
12
</td>
<td  class="td_bit">
11
</td>
<td  class="td_bit">
10
</td>
<td  class="td_bit">
9
</td>
<td  class="td_bit">
8
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8  class="td_field">
MAC_LOCAL_MSB[15:8]
</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td  class="td_bit">
7
</td>
<td  class="td_bit">
6
</td>
<td  class="td_bit">
5
</td>
<td  class="td_bit">
4
</td>
<td  class="td_bit">
3
</td>
<td  class="td_bit">
2
</td>
<td  class="td_bit">
1
</td>
<td  class="td_bit">
0
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8  class="td_field">
MAC_LOCAL_MSB[7:0]
</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
</tr>
</table>
<ul>
<li><b>
MAC_LOCAL_MSB
</b>[<i>read/write</i>]: MAC Local MSB
</ul>
<a name="TX_CFG3"></a>
<h3><a name="sect_3_15">3.15. Tx Config Reg 3</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td  class="td_code">
wr_transmission_tx_cfg3
</td>
</tr>
<tr>
<td >
<b>HW address: </b>
</td>
<td  class="td_code">
0xe
</td>
</tr>
<tr>
<td >
<b>C prefix: </b>
</td>
<td  class="td_code">
TX_CFG3
</td>
</tr>
<tr>
<td >
<b>C offset: </b>
</td>
<td  class="td_code">
0x38
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td  class="td_bit">
31
</td>
<td  class="td_bit">
30
</td>
<td  class="td_bit">
29
</td>
<td  class="td_bit">
28
</td>
<td  class="td_bit">
27
</td>
<td  class="td_bit">
26
</td>
<td  class="td_bit">
25
</td>
<td  class="td_bit">
24
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8  class="td_field">
MAC_TARGET_LSB[31:24]
</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td  class="td_bit">
23
</td>
<td  class="td_bit">
22
</td>
<td  class="td_bit">
21
</td>
<td  class="td_bit">
20
</td>
<td  class="td_bit">
19
</td>
<td  class="td_bit">
18
</td>
<td  class="td_bit">
17
</td>
<td  class="td_bit">
16
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8  class="td_field">
MAC_TARGET_LSB[23:16]
</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td  class="td_bit">
15
</td>
<td  class="td_bit">
14
</td>
<td  class="td_bit">
13
</td>
<td  class="td_bit">
12
</td>
<td  class="td_bit">
11
</td>
<td  class="td_bit">
10
</td>
<td  class="td_bit">
9
</td>
<td  class="td_bit">
8
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8  class="td_field">
MAC_TARGET_LSB[15:8]
</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td  class="td_bit">
7
</td>
<td  class="td_bit">
6
</td>
<td  class="td_bit">
5
</td>
<td  class="td_bit">
4
</td>
<td  class="td_bit">
3
</td>
<td  class="td_bit">
2
</td>
<td  class="td_bit">
1
</td>
<td  class="td_bit">
0
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8  class="td_field">
MAC_TARGET_LSB[7:0]
</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
</tr>
</table>
<ul>
<li><b>
MAC_TARGET_LSB
</b>[<i>read/write</i>]: MAC Target LSB
</ul>
<a name="TX_CFG4"></a>
<h3><a name="sect_3_16">3.16. Tx Config Reg 4</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td  class="td_code">
wr_transmission_tx_cfg4
</td>
</tr>
<tr>
<td >
<b>HW address: </b>
</td>
<td  class="td_code">
0xf
</td>
</tr>
<tr>
<td >
<b>C prefix: </b>
</td>
<td  class="td_code">
TX_CFG4
</td>
</tr>
<tr>
<td >
<b>C offset: </b>
</td>
<td  class="td_code">
0x3c
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td  class="td_bit">
31
</td>
<td  class="td_bit">
30
</td>
<td  class="td_bit">
29
</td>
<td  class="td_bit">
28
</td>
<td  class="td_bit">
27
</td>
<td  class="td_bit">
26
</td>
<td  class="td_bit">
25
</td>
<td  class="td_bit">
24
</td>
</tr>
<tr>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td  class="td_bit">
23
</td>
<td  class="td_bit">
22
</td>
<td  class="td_bit">
21
</td>
<td  class="td_bit">
20
</td>
<td  class="td_bit">
19
</td>
<td  class="td_bit">
18
</td>
<td  class="td_bit">
17
</td>
<td  class="td_bit">
16
</td>
</tr>
<tr>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td  class="td_bit">
15
</td>
<td  class="td_bit">
14
</td>
<td  class="td_bit">
13
</td>
<td  class="td_bit">
12
</td>
<td  class="td_bit">
11
</td>
<td  class="td_bit">
10
</td>
<td  class="td_bit">
9
</td>
<td  class="td_bit">
8
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8  class="td_field">
MAC_TARGET_MSB[15:8]
</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td  class="td_bit">
7
</td>
<td  class="td_bit">
6
</td>
<td  class="td_bit">
5
</td>
<td  class="td_bit">
4
</td>
<td  class="td_bit">
3
</td>
<td  class="td_bit">
2
</td>
<td  class="td_bit">
1
</td>
<td  class="td_bit">
0
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8  class="td_field">
MAC_TARGET_MSB[7:0]
</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
</tr>
</table>
<ul>
<li><b>
MAC_TARGET_MSB
</b>[<i>read/write</i>]: MAC Target MSB
</ul>
<a name="RX_CFG0"></a>
<h3><a name="sect_3_17">3.17. Rx Config Reg 0</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td  class="td_code">
wr_transmission_rx_cfg0
</td>
</tr>
<tr>
<td >
<b>HW address: </b>
</td>
<td  class="td_code">
0x10
</td>
</tr>
<tr>
<td >
<b>C prefix: </b>
</td>
<td  class="td_code">
RX_CFG0
</td>
</tr>
<tr>
<td >
<b>C offset: </b>
</td>
<td  class="td_code">
0x40
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td  class="td_bit">
31
</td>
<td  class="td_bit">
30
</td>
<td  class="td_bit">
29
</td>
<td  class="td_bit">
28
</td>
<td  class="td_bit">
27
</td>
<td  class="td_bit">
26
</td>
<td  class="td_bit">
25
</td>
<td  class="td_bit">
24
</td>
</tr>
<tr>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td  class="td_bit">
23
</td>
<td  class="td_bit">
22
</td>
<td  class="td_bit">
21
</td>
<td  class="td_bit">
20
</td>
<td  class="td_bit">
19
</td>
<td  class="td_bit">
18
</td>
<td  class="td_bit">
17
</td>
<td  class="td_bit">
16
</td>
</tr>
<tr>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td style="border: solid 1px black;" colspan=1  class="td_field">
FILTER_REMOTE
</td>
<td style="border: solid 1px black;" colspan=1  class="td_field">
ACCEPT_BROADCAST
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td  class="td_bit">
15
</td>
<td  class="td_bit">
14
</td>
<td  class="td_bit">
13
</td>
<td  class="td_bit">
12
</td>
<td  class="td_bit">
11
</td>
<td  class="td_bit">
10
</td>
<td  class="td_bit">
9
</td>
<td  class="td_bit">
8
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8  class="td_field">
ETHERTYPE[15:8]
</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td  class="td_bit">
7
</td>
<td  class="td_bit">
6
</td>
<td  class="td_bit">
5
</td>
<td  class="td_bit">
4
</td>
<td  class="td_bit">
3
</td>
<td  class="td_bit">
2
</td>
<td  class="td_bit">
1
</td>
<td  class="td_bit">
0
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8  class="td_field">
ETHERTYPE[7:0]
</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
</tr>
</table>
<ul>
<li><b>
ETHERTYPE
</b>[<i>read/write</i>]: Ethertype
<li><b>
ACCEPT_BROADCAST
</b>[<i>read/write</i>]: Accept Broadcast
<br>0: accept only unicasts; <br>      1: accept all broadcast packets
<li><b>
FILTER_REMOTE
</b>[<i>read/write</i>]: Filter Remote
<br>0: accept streamer frames with any source MAC address; <br>      1: accept streamer frames only with the source MAC address defined in mac_remote
</ul>
<a name="RX_CFG1"></a>
<h3><a name="sect_3_18">3.18. Rx Config Reg 1</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td  class="td_code">
wr_transmission_rx_cfg1
</td>
</tr>
<tr>
<td >
<b>HW address: </b>
</td>
<td  class="td_code">
0x11
</td>
</tr>
<tr>
<td >
<b>C prefix: </b>
</td>
<td  class="td_code">
RX_CFG1
</td>
</tr>
<tr>
<td >
<b>C offset: </b>
</td>
<td  class="td_code">
0x44
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td  class="td_bit">
31
</td>
<td  class="td_bit">
30
</td>
<td  class="td_bit">
29
</td>
<td  class="td_bit">
28
</td>
<td  class="td_bit">
27
</td>
<td  class="td_bit">
26
</td>
<td  class="td_bit">
25
</td>
<td  class="td_bit">
24
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8  class="td_field">
MAC_LOCAL_LSB[31:24]
</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td  class="td_bit">
23
</td>
<td  class="td_bit">
22
</td>
<td  class="td_bit">
21
</td>
<td  class="td_bit">
20
</td>
<td  class="td_bit">
19
</td>
<td  class="td_bit">
18
</td>
<td  class="td_bit">
17
</td>
<td  class="td_bit">
16
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8  class="td_field">
MAC_LOCAL_LSB[23:16]
</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td  class="td_bit">
15
</td>
<td  class="td_bit">
14
</td>
<td  class="td_bit">
13
</td>
<td  class="td_bit">
12
</td>
<td  class="td_bit">
11
</td>
<td  class="td_bit">
10
</td>
<td  class="td_bit">
9
</td>
<td  class="td_bit">
8
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8  class="td_field">
MAC_LOCAL_LSB[15:8]
</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td  class="td_bit">
7
</td>
<td  class="td_bit">
6
</td>
<td  class="td_bit">
5
</td>
<td  class="td_bit">
4
</td>
<td  class="td_bit">
3
</td>
<td  class="td_bit">
2
</td>
<td  class="td_bit">
1
</td>
<td  class="td_bit">
0
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8  class="td_field">
MAC_LOCAL_LSB[7:0]
</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
</tr>
</table>
<ul>
<li><b>
MAC_LOCAL_LSB
</b>[<i>read/write</i>]: MAC Local LSB
</ul>
<a name="RX_CFG2"></a>
<h3><a name="sect_3_19">3.19. Rx Config Reg 2</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td  class="td_code">
wr_transmission_rx_cfg2
</td>
</tr>
<tr>
<td >
<b>HW address: </b>
</td>
<td  class="td_code">
0x12
</td>
</tr>
<tr>
<td >
<b>C prefix: </b>
</td>
<td  class="td_code">
RX_CFG2
</td>
</tr>
<tr>
<td >
<b>C offset: </b>
</td>
<td  class="td_code">
0x48
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td  class="td_bit">
31
</td>
<td  class="td_bit">
30
</td>
<td  class="td_bit">
29
</td>
<td  class="td_bit">
28
</td>
<td  class="td_bit">
27
</td>
<td  class="td_bit">
26
</td>
<td  class="td_bit">
25
</td>
<td  class="td_bit">
24
</td>
</tr>
<tr>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td  class="td_bit">
23
</td>
<td  class="td_bit">
22
</td>
<td  class="td_bit">
21
</td>
<td  class="td_bit">
20
</td>
<td  class="td_bit">
19
</td>
<td  class="td_bit">
18
</td>
<td  class="td_bit">
17
</td>
<td  class="td_bit">
16
</td>
</tr>
<tr>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td  class="td_bit">
15
</td>
<td  class="td_bit">
14
</td>
<td  class="td_bit">
13
</td>
<td  class="td_bit">
12
</td>
<td  class="td_bit">
11
</td>
<td  class="td_bit">
10
</td>
<td  class="td_bit">
9
</td>
<td  class="td_bit">
8
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8  class="td_field">
MAC_LOCAL_MSB[15:8]
</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td  class="td_bit">
7
</td>
<td  class="td_bit">
6
</td>
<td  class="td_bit">
5
</td>
<td  class="td_bit">
4
</td>
<td  class="td_bit">
3
</td>
<td  class="td_bit">
2
</td>
<td  class="td_bit">
1
</td>
<td  class="td_bit">
0
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8  class="td_field">
MAC_LOCAL_MSB[7:0]
</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
</tr>
</table>
<ul>
<li><b>
MAC_LOCAL_MSB
</b>[<i>read/write</i>]: MAC Local MSB
</ul>
<a name="RX_CFG3"></a>
<h3><a name="sect_3_20">3.20. Rx Config Reg 3</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td  class="td_code">
wr_transmission_rx_cfg3
</td>
</tr>
<tr>
<td >
<b>HW address: </b>
</td>
<td  class="td_code">
0x13
</td>
</tr>
<tr>
<td >
<b>C prefix: </b>
</td>
<td  class="td_code">
RX_CFG3
</td>
</tr>
<tr>
<td >
<b>C offset: </b>
</td>
<td  class="td_code">
0x4c
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td  class="td_bit">
31
</td>
<td  class="td_bit">
30
</td>
<td  class="td_bit">
29
</td>
<td  class="td_bit">
28
</td>
<td  class="td_bit">
27
</td>
<td  class="td_bit">
26
</td>
<td  class="td_bit">
25
</td>
<td  class="td_bit">
24
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8  class="td_field">
MAC_REMOTE_LSB[31:24]
</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td  class="td_bit">
23
</td>
<td  class="td_bit">
22
</td>
<td  class="td_bit">
21
</td>
<td  class="td_bit">
20
</td>
<td  class="td_bit">
19
</td>
<td  class="td_bit">
18
</td>
<td  class="td_bit">
17
</td>
<td  class="td_bit">
16
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8  class="td_field">
MAC_REMOTE_LSB[23:16]
</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td  class="td_bit">
15
</td>
<td  class="td_bit">
14
</td>
<td  class="td_bit">
13
</td>
<td  class="td_bit">
12
</td>
<td  class="td_bit">
11
</td>
<td  class="td_bit">
10
</td>
<td  class="td_bit">
9
</td>
<td  class="td_bit">
8
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8  class="td_field">
MAC_REMOTE_LSB[15:8]
</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td  class="td_bit">
7
</td>
<td  class="td_bit">
6
</td>
<td  class="td_bit">
5
</td>
<td  class="td_bit">
4
</td>
<td  class="td_bit">
3
</td>
<td  class="td_bit">
2
</td>
<td  class="td_bit">
1
</td>
<td  class="td_bit">
0
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8  class="td_field">
MAC_REMOTE_LSB[7:0]
</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
</tr>
</table>
<ul>
<li><b>
MAC_REMOTE_LSB
</b>[<i>read/write</i>]: MAC Remote LSB
</ul>
<a name="RX_CFG4"></a>
<h3><a name="sect_3_21">3.21. Rx Config Reg 4</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td  class="td_code">
wr_transmission_rx_cfg4
</td>
</tr>
<tr>
<td >
<b>HW address: </b>
</td>
<td  class="td_code">
0x14
</td>
</tr>
<tr>
<td >
<b>C prefix: </b>
</td>
<td  class="td_code">
RX_CFG4
</td>
</tr>
<tr>
<td >
<b>C offset: </b>
</td>
<td  class="td_code">
0x50
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td  class="td_bit">
31
</td>
<td  class="td_bit">
30
</td>
<td  class="td_bit">
29
</td>
<td  class="td_bit">
28
</td>
<td  class="td_bit">
27
</td>
<td  class="td_bit">
26
</td>
<td  class="td_bit">
25
</td>
<td  class="td_bit">
24
</td>
</tr>
<tr>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td  class="td_bit">
23
</td>
<td  class="td_bit">
22
</td>
<td  class="td_bit">
21
</td>
<td  class="td_bit">
20
</td>
<td  class="td_bit">
19
</td>
<td  class="td_bit">
18
</td>
<td  class="td_bit">
17
</td>
<td  class="td_bit">
16
</td>
</tr>
<tr>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td  class="td_bit">
15
</td>
<td  class="td_bit">
14
</td>
<td  class="td_bit">
13
</td>
<td  class="td_bit">
12
</td>
<td  class="td_bit">
11
</td>
<td  class="td_bit">
10
</td>
<td  class="td_bit">
9
</td>
<td  class="td_bit">
8
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8  class="td_field">
MAC_REMOTE_MSB[15:8]
</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td  class="td_bit">
7
</td>
<td  class="td_bit">
6
</td>
<td  class="td_bit">
5
</td>
<td  class="td_bit">
4
</td>
<td  class="td_bit">
3
</td>
<td  class="td_bit">
2
</td>
<td  class="td_bit">
1
</td>
<td  class="td_bit">
0
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8  class="td_field">
MAC_REMOTE_MSB[7:0]
</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
</tr>
</table>
<ul>
<li><b>
MAC_REMOTE_MSB
</b>[<i>read/write</i>]: MAC Remote MSB
</ul>
<a name="RX_CFG5"></a>
<h3><a name="sect_3_22">3.22. Rx Config Reg 5</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td  class="td_code">
wr_transmission_rx_cfg5
</td>
</tr>
<tr>
<td >
<b>HW address: </b>
</td>
<td  class="td_code">
0x15
</td>
</tr>
<tr>
<td >
<b>C prefix: </b>
</td>
<td  class="td_code">
RX_CFG5
</td>
</tr>
<tr>
<td >
<b>C offset: </b>
</td>
<td  class="td_code">
0x54
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td  class="td_bit">
31
</td>
<td  class="td_bit">
30
</td>
<td  class="td_bit">
29
</td>
<td  class="td_bit">
28
</td>
<td  class="td_bit">
27
</td>
<td  class="td_bit">
26
</td>
<td  class="td_bit">
25
</td>
<td  class="td_bit">
24
</td>
</tr>
<tr>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td style="border: solid 1px black;" colspan=4  class="td_field">
FIXED_LATENCY[27:24]
</td>
<td >

</td>
<td >

</td>
<td >

</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td  class="td_bit">
23
</td>
<td  class="td_bit">
22
</td>
<td  class="td_bit">
21
</td>
<td  class="td_bit">
20
</td>
<td  class="td_bit">
19
</td>
<td  class="td_bit">
18
</td>
<td  class="td_bit">
17
</td>
<td  class="td_bit">
16
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8  class="td_field">
FIXED_LATENCY[23:16]
</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td  class="td_bit">
15
</td>
<td  class="td_bit">
14
</td>
<td  class="td_bit">
13
</td>
<td  class="td_bit">
12
</td>
<td  class="td_bit">
11
</td>
<td  class="td_bit">
10
</td>
<td  class="td_bit">
9
</td>
<td  class="td_bit">
8
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8  class="td_field">
FIXED_LATENCY[15:8]
</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td  class="td_bit">
7
</td>
<td  class="td_bit">
6
</td>
<td  class="td_bit">
5
</td>
<td  class="td_bit">
4
</td>
<td  class="td_bit">
3
</td>
<td  class="td_bit">
2
</td>
<td  class="td_bit">
1
</td>
<td  class="td_bit">
0
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8  class="td_field">
FIXED_LATENCY[7:0]
</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
</tr>
</table>
<ul>
<li><b>
FIXED_LATENCY
</b>[<i>read/write</i>]: Fixed Latency
<br>This register allows to configure fixed-latency. If the value is other than zero, the instant of outputing the received data from the rx streamer to the user application is delayed, so that the time-difference between the transmission fo the data and the output to the user matches the provided value. If the configured latency value is smaller than the network latency, the data is provided to the user instantly. The configuration value is expressed in clock cycles (16ns) 
</ul>
<a name="CFG"></a>
<h3><a name="sect_3_23">3.23. TxRx Config Override</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td  class="td_code">
wr_transmission_cfg
</td>
</tr>
<tr>
<td >
<b>HW address: </b>
</td>
<td  class="td_code">
0x16
</td>
</tr>
<tr>
<td >
<b>C prefix: </b>
</td>
<td  class="td_code">
CFG
</td>
</tr>
<tr>
<td >
<b>C offset: </b>
</td>
<td  class="td_code">
0x58
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td  class="td_bit">
31
</td>
<td  class="td_bit">
30
</td>
<td  class="td_bit">
29
</td>
<td  class="td_bit">
28
</td>
<td  class="td_bit">
27
</td>
<td  class="td_bit">
26
</td>
<td  class="td_bit">
25
</td>
<td  class="td_bit">
24
</td>
</tr>
<tr>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td  class="td_bit">
23
</td>
<td  class="td_bit">
22
</td>
<td  class="td_bit">
21
</td>
<td  class="td_bit">
20
</td>
<td  class="td_bit">
19
</td>
<td  class="td_bit">
18
</td>
<td  class="td_bit">
17
</td>
<td  class="td_bit">
16
</td>
</tr>
<tr>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td style="border: solid 1px black;" colspan=1  class="td_field">
OR_RX_FIX_LAT
</td>
<td style="border: solid 1px black;" colspan=1  class="td_field">
OR_RX_FTR_REMOTE
</td>
<td style="border: solid 1px black;" colspan=1  class="td_field">
OR_RX_ACC_BROADCAST
</td>
<td style="border: solid 1px black;" colspan=1  class="td_field">
OR_RX_MAC_REM
</td>
<td style="border: solid 1px black;" colspan=1  class="td_field">
OR_RX_MAC_LOC
</td>
<td style="border: solid 1px black;" colspan=1  class="td_field">
OR_RX_ETHERTYPE
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td  class="td_bit">
15
</td>
<td  class="td_bit">
14
</td>
<td  class="td_bit">
13
</td>
<td  class="td_bit">
12
</td>
<td  class="td_bit">
11
</td>
<td  class="td_bit">
10
</td>
<td  class="td_bit">
9
</td>
<td  class="td_bit">
8
</td>
</tr>
<tr>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td  class="td_bit">
7
</td>
<td  class="td_bit">
6
</td>
<td  class="td_bit">
5
</td>
<td  class="td_bit">
4
</td>
<td  class="td_bit">
3
</td>
<td  class="td_bit">
2
</td>
<td  class="td_bit">
1
</td>
<td  class="td_bit">
0
</td>
</tr>
<tr>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td style="border: solid 1px black;" colspan=1  class="td_field">
OR_TX_MAC_TAR
</td>
<td style="border: solid 1px black;" colspan=1  class="td_field">
OR_TX_MAC_LOC
</td>
<td style="border: solid 1px black;" colspan=1  class="td_field">
OR_TX_ETHTYPE
</td>
</tr>
</table>
<ul>
<li><b>
OR_TX_ETHTYPE
</b>[<i>read/write</i>]: Tx Ethertype
<br>Overrides default/application Tx Ethertype configuration with configuration in the proper register:<br>      0: Default/set by application; <br>      1: Value from WB register
<li><b>
OR_TX_MAC_LOC
</b>[<i>read/write</i>]: Tx MAC Local
<br>Overrides default/application Tx local MAC configuration with configuration in the proper register:<br>      0: Default/set by application; <br>      1: Value from WB register
<li><b>
OR_TX_MAC_TAR
</b>[<i>read/write</i>]: Tx MAC Target
<br>Overrides default/application Tx target MAC configuration with configuration in the proper register:<br>      0: Default/set by application; <br>      1: Value from WB register
<li><b>
OR_RX_ETHERTYPE
</b>[<i>read/write</i>]: Rx Ethertype
<br>Overrides default/application Rx Ethertype configuration with configuration in the proper register:<br>      0: Default/set by application; <br>      1: Value from WB register
<li><b>
OR_RX_MAC_LOC
</b>[<i>read/write</i>]: Rx MAC Local
<br>Overrides default/application Rx MAC Local configuration with configuration in the proper register:<br>      0: Default/set by application; <br>      1: Value from WB register
<li><b>
OR_RX_MAC_REM
</b>[<i>read/write</i>]: Rx MAC Remote
<br>Overrides default/application Rx MAC Remote configuration with configuration in the proper register:<br>      0: Default/set by application; <br>      1: Value from WB register
<li><b>
OR_RX_ACC_BROADCAST
</b>[<i>read/write</i>]: Rx Accept Broadcast
<br>Overrides default/application Rx Accept Broardcast configuration with configuration in the proper register:<br>      0: Default/set by application; <br>      1: Value from WB register
<li><b>
OR_RX_FTR_REMOTE
</b>[<i>read/write</i>]: Rx Filter Remote
<br>Overrides default/application Rx Filter Remote configuration with configuration in the proper register:<br>      0: Default/set by application; <br>      1: Value from WB register
<li><b>
OR_RX_FIX_LAT
</b>[<i>read/write</i>]: Rx Fixed Latency 
<br>Overrides default/application Rx fixed latency configuration with configuration in the proper register:<br>      0: Default/set by application; <br>      1: Value from WB register
</ul>
<a name="DBG_CTRL"></a>
<h3><a name="sect_3_24">3.24. DBG Control register</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td  class="td_code">
wr_transmission_dbg_ctrl
</td>
</tr>
<tr>
<td >
<b>HW address: </b>
</td>
<td  class="td_code">
0x17
</td>
</tr>
<tr>
<td >
<b>C prefix: </b>
</td>
<td  class="td_code">
DBG_CTRL
</td>
</tr>
<tr>
<td >
<b>C offset: </b>
</td>
<td  class="td_code">
0x5c
</td>
</tr>
</table>
<p>
This register is meant to control simple debugging of transmitted or received data.<br>    It allows to sniff a 32-bit word at a configurable offset from received or transmitted data.
</p>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td  class="td_bit">
31
</td>
<td  class="td_bit">
30
</td>
<td  class="td_bit">
29
</td>
<td  class="td_bit">
28
</td>
<td  class="td_bit">
27
</td>
<td  class="td_bit">
26
</td>
<td  class="td_bit">
25
</td>
<td  class="td_bit">
24
</td>
</tr>
<tr>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td  class="td_bit">
23
</td>
<td  class="td_bit">
22
</td>
<td  class="td_bit">
21
</td>
<td  class="td_bit">
20
</td>
<td  class="td_bit">
19
</td>
<td  class="td_bit">
18
</td>
<td  class="td_bit">
17
</td>
<td  class="td_bit">
16
</td>
</tr>
<tr>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td  class="td_bit">
15
</td>
<td  class="td_bit">
14
</td>
<td  class="td_bit">
13
</td>
<td  class="td_bit">
12
</td>
<td  class="td_bit">
11
</td>
<td  class="td_bit">
10
</td>
<td  class="td_bit">
9
</td>
<td  class="td_bit">
8
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8  class="td_field">
START_BYTE[7:0]
</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td  class="td_bit">
7
</td>
<td  class="td_bit">
6
</td>
<td  class="td_bit">
5
</td>
<td  class="td_bit">
4
</td>
<td  class="td_bit">
3
</td>
<td  class="td_bit">
2
</td>
<td  class="td_bit">
1
</td>
<td  class="td_bit">
0
</td>
</tr>
<tr>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td style="border: solid 1px black;" colspan=1  class="td_field">
MUX
</td>
</tr>
</table>
<ul>
<li><b>
MUX
</b>[<i>read/write</i>]: Debug Tx (0) or Rx (1)
<li><b>
START_BYTE
</b>[<i>read/write</i>]: Debug Start byte
<br>The offset, in bytes, from which the 32-bit word is read.
</ul>
<a name="DBG_DATA"></a>
<h3><a name="sect_3_25">3.25. DBG Data</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td  class="td_code">
wr_transmission_dbg_data
</td>
</tr>
<tr>
<td >
<b>HW address: </b>
</td>
<td  class="td_code">
0x18
</td>
</tr>
<tr>
<td >
<b>C prefix: </b>
</td>
<td  class="td_code">
DBG_DATA
</td>
</tr>
<tr>
<td >
<b>C offset: </b>
</td>
<td  class="td_code">
0x60
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td  class="td_bit">
31
</td>
<td  class="td_bit">
30
</td>
<td  class="td_bit">
29
</td>
<td  class="td_bit">
28
</td>
<td  class="td_bit">
27
</td>
<td  class="td_bit">
26
</td>
<td  class="td_bit">
25
</td>
<td  class="td_bit">
24
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8  class="td_field">
DBG_DATA[31:24]
</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td  class="td_bit">
23
</td>
<td  class="td_bit">
22
</td>
<td  class="td_bit">
21
</td>
<td  class="td_bit">
20
</td>
<td  class="td_bit">
19
</td>
<td  class="td_bit">
18
</td>
<td  class="td_bit">
17
</td>
<td  class="td_bit">
16
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8  class="td_field">
DBG_DATA[23:16]
</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td  class="td_bit">
15
</td>
<td  class="td_bit">
14
</td>
<td  class="td_bit">
13
</td>
<td  class="td_bit">
12
</td>
<td  class="td_bit">
11
</td>
<td  class="td_bit">
10
</td>
<td  class="td_bit">
9
</td>
<td  class="td_bit">
8
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8  class="td_field">
DBG_DATA[15:8]
</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td  class="td_bit">
7
</td>
<td  class="td_bit">
6
</td>
<td  class="td_bit">
5
</td>
<td  class="td_bit">
4
</td>
<td  class="td_bit">
3
</td>
<td  class="td_bit">
2
</td>
<td  class="td_bit">
1
</td>
<td  class="td_bit">
0
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8  class="td_field">
DBG_DATA[7:0]
</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
</tr>
</table>
<ul>
<li><b>
DBG_DATA
</b>[<i>read-only</i>]: Debug content
</ul>
<a name="DBG_RX_BVALUE"></a>
<h3><a name="sect_3_26">3.26. DBG RX_BVALUE</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td  class="td_code">
wr_transmission_dbg_rx_bvalue
</td>
</tr>
<tr>
<td >
<b>HW address: </b>
</td>
<td  class="td_code">
0x19
</td>
</tr>
<tr>
<td >
<b>C prefix: </b>
</td>
<td  class="td_code">
DBG_RX_BVALUE
</td>
</tr>
<tr>
<td >
<b>C offset: </b>
</td>
<td  class="td_code">
0x64
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td  class="td_bit">
31
</td>
<td  class="td_bit">
30
</td>
<td  class="td_bit">
29
</td>
<td  class="td_bit">
28
</td>
<td  class="td_bit">
27
</td>
<td  class="td_bit">
26
</td>
<td  class="td_bit">
25
</td>
<td  class="td_bit">
24
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8  class="td_field">
DBG_RX_BVALUE[31:24]
</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td  class="td_bit">
23
</td>
<td  class="td_bit">
22
</td>
<td  class="td_bit">
21
</td>
<td  class="td_bit">
20
</td>
<td  class="td_bit">
19
</td>
<td  class="td_bit">
18
</td>
<td  class="td_bit">
17
</td>
<td  class="td_bit">
16
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8  class="td_field">
DBG_RX_BVALUE[23:16]
</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td  class="td_bit">
15
</td>
<td  class="td_bit">
14
</td>
<td  class="td_bit">
13
</td>
<td  class="td_bit">
12
</td>
<td  class="td_bit">
11
</td>
<td  class="td_bit">
10
</td>
<td  class="td_bit">
9
</td>
<td  class="td_bit">
8
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8  class="td_field">
DBG_RX_BVALUE[15:8]
</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td  class="td_bit">
7
</td>
<td  class="td_bit">
6
</td>
<td  class="td_bit">
5
</td>
<td  class="td_bit">
4
</td>
<td  class="td_bit">
3
</td>
<td  class="td_bit">
2
</td>
<td  class="td_bit">
1
</td>
<td  class="td_bit">
0
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8  class="td_field">
DBG_RX_BVALUE[7:0]
</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
</tr>
</table>
<ul>
<li><b>
DBG_RX_BVALUE
</b>[<i>read-only</i>]: Debug content
</ul>
<a name="DBG_TX_BVALUE"></a>
<h3><a name="sect_3_27">3.27. DBG tx bvalue</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td  class="td_code">
wr_transmission_dbg_tx_bvalue
</td>
</tr>
<tr>
<td >
<b>HW address: </b>
</td>
<td  class="td_code">
0x1a
</td>
</tr>
<tr>
<td >
<b>C prefix: </b>
</td>
<td  class="td_code">
DBG_TX_BVALUE
</td>
</tr>
<tr>
<td >
<b>C offset: </b>
</td>
<td  class="td_code">
0x68
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td  class="td_bit">
31
</td>
<td  class="td_bit">
30
</td>
<td  class="td_bit">
29
</td>
<td  class="td_bit">
28
</td>
<td  class="td_bit">
27
</td>
<td  class="td_bit">
26
</td>
<td  class="td_bit">
25
</td>
<td  class="td_bit">
24
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8  class="td_field">
DBG_TX_BVALUE[31:24]
</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td  class="td_bit">
23
</td>
<td  class="td_bit">
22
</td>
<td  class="td_bit">
21
</td>
<td  class="td_bit">
20
</td>
<td  class="td_bit">
19
</td>
<td  class="td_bit">
18
</td>
<td  class="td_bit">
17
</td>
<td  class="td_bit">
16
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8  class="td_field">
DBG_TX_BVALUE[23:16]
</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td  class="td_bit">
15
</td>
<td  class="td_bit">
14
</td>
<td  class="td_bit">
13
</td>
<td  class="td_bit">
12
</td>
<td  class="td_bit">
11
</td>
<td  class="td_bit">
10
</td>
<td  class="td_bit">
9
</td>
<td  class="td_bit">
8
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8  class="td_field">
DBG_TX_BVALUE[15:8]
</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td  class="td_bit">
7
</td>
<td  class="td_bit">
6
</td>
<td  class="td_bit">
5
</td>
<td  class="td_bit">
4
</td>
<td  class="td_bit">
3
</td>
<td  class="td_bit">
2
</td>
<td  class="td_bit">
1
</td>
<td  class="td_bit">
0
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8  class="td_field">
DBG_TX_BVALUE[7:0]
</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
</tr>
</table>
<ul>
<li><b>
DBG_TX_BVALUE
</b>[<i>read-only</i>]: Debug content
</ul>
<a name="DUMMY"></a>
<h3><a name="sect_3_28">3.28. Test value</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td  class="td_code">
wr_transmission_dummy
</td>
</tr>
<tr>
<td >
<b>HW address: </b>
</td>
<td  class="td_code">
0x1b
</td>
</tr>
<tr>
<td >
<b>C prefix: </b>
</td>
<td  class="td_code">
DUMMY
</td>
</tr>
<tr>
<td >
<b>C offset: </b>
</td>
<td  class="td_code">
0x6c
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td  class="td_bit">
31
</td>
<td  class="td_bit">
30
</td>
<td  class="td_bit">
29
</td>
<td  class="td_bit">
28
</td>
<td  class="td_bit">
27
</td>
<td  class="td_bit">
26
</td>
<td  class="td_bit">
25
</td>
<td  class="td_bit">
24
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8  class="td_field">
DUMMY[31:24]
</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td  class="td_bit">
23
</td>
<td  class="td_bit">
22
</td>
<td  class="td_bit">
21
</td>
<td  class="td_bit">
20
</td>
<td  class="td_bit">
19
</td>
<td  class="td_bit">
18
</td>
<td  class="td_bit">
17
</td>
<td  class="td_bit">
16
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8  class="td_field">
DUMMY[23:16]
</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td  class="td_bit">
15
</td>
<td  class="td_bit">
14
</td>
<td  class="td_bit">
13
</td>
<td  class="td_bit">
12
</td>
<td  class="td_bit">
11
</td>
<td  class="td_bit">
10
</td>
<td  class="td_bit">
9
</td>
<td  class="td_bit">
8
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8  class="td_field">
DUMMY[15:8]
</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td  class="td_bit">
7
</td>
<td  class="td_bit">
6
</td>
<td  class="td_bit">
5
</td>
<td  class="td_bit">
4
</td>
<td  class="td_bit">
3
</td>
<td  class="td_bit">
2
</td>
<td  class="td_bit">
1
</td>
<td  class="td_bit">
0
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8  class="td_field">
DUMMY[7:0]
</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
</tr>
</table>
<ul>
<li><b>
DUMMY
</b>[<i>read-only</i>]: DUMMY value to read
</ul>



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